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ds07-16307-1e fujitsu semiconductor data sheet 32-bit risc microcontroller cmos fr family MB91110 series MB91110/mb91v110 n n n n description the MB91110 series is a standard single-chip micro controller featuring various i/o resources and bus control mechanisms to incorporate the control with required for high performance high-speed cpu processes, having a 32-bit risc cpu (fr30 series) in its core. although external bus access is the basis for supporting a large address space accessible by a 32-bit cpu, a 1-kb instruction cache memory has been built-in to increase the instruction/ execution speed of the cpu. this unit features the optimal specifications for incorporating applications that require high performance cpu processing power such as navigation systems, high performance facsimile systems, printer control, etc. n n n n features fr30cpu ? 32-bit risc, load / store architecture, 5-level pipeline ? operating frequency : external 25 mhz, internal 50 mhz ? multi-purpose register : 32 bits 16 ? 16-bit fixed length instructions (basic instruction) , 1 instruction per cycle ? instructions for barrel shift, bit processing and inter memory transfers : instructions suited to loading purposes ? function entry / exit instruction, multi load / store instruction of register details : instruction capable of handling high level language instruction. ? register interlock function : simplification of assembler description (continued) n n n n pac k ag e 144-pin plastic lqfp (fpt-144p-m08)
MB91110 series 2 (continued) ? branch instruction with delay slot : reduction in overheads in case of branching ? multiplier is built-in / supported at instruction level signed 32-bit multiplication : 5 cycles signed 16-bit multiplication : 3 cycles ? interruption (saving pc and ps) : 6 cycles, 16 priority levels bus interface ? 24-bit address bus (16 mb space) ? operating frequency : 25 mhz ? 16- / 8-bit data bus ? basic external bus cycle : 2 clock cycles ? chip select output that can be set to a minimum 64-kbyte units ? interface support for various memories dram interface (areas 4, 5) ? automatic waiting cycle : can be randomly set from 0 to 7 cycles per area ? unused data and address pins can be used as input/output ports. ? supports little endian mode (one area is selected from areas 1 to 5) dram interface ? 2-bank individual control (area 4, 5) ? normal mode / high speed page mode ? basic bus cycles : normally 5 cycles, 1 cycle access is possible in high-speed page mode. ? programmable waveform : 1 cycle waiting can be inserted automatically in ras and cas. ?dram refresh cbr refresh (interval is randomly set using the 6-bit timer.) self refresh mode ? supports addresses for 8, 9, 10 and 12 columns ? 2cas/1we or 2we/1cas can be selected. cache memory ? 1 kb instruction cache ? 2 way set associative ? 32 blocks / way, 4 entries (4 words) / block ? lock function : residing in the specified program codes at cache dma controller (dmac) ? 5 channels ? external ? external 2.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle) ? internal ? external 1.5 access cycles / transfer (if 2 clock cycles are defined as 1 access cycle) ? address register (inc, dec, or reload are possible) : 32 bits 5 channels ? transfer count register (reload possible) : 16 bits 5 channels ? transfer factors : external pin / built-in resources interruption request / software ? transfer sequence step transfer / block transfer burst / consecutive transfer ? transfer data length : 8-bit, 16-bit or 32-bit can be selected ? suspension is possible using nmi / interruption request uart ? fully duplicated double buffer ? data length : 7 to 9 bits (without parity) , 6 to 8 bits (with parity)
MB91110 series 3 ? asynchronous (start-stop synchronization) or clk synchronized communication can be selected. ? multiprocessor mode ? dedicated baud rate generator is built-in. ? external clock can be used as the transfer clock ? baud rate clock can be output ? error detection : parity, frame, overrun ppg timer ? 16 bits, 6 channels (frequency setting register / duty setting register) ? pwm function or one-shot function can be selected ? initiation : software or external trigger can be selected a / d converter (sequential conversion type) ? 10-bit resolution, 8 channels ? sequential comparison conversion : 5.6 m s in the case of 25 mhz ? sample & hold circuit is built-in. ? conversion mode : single, scan or repeat conversion can be selected. ? initiation : software, external trigger or built-in timer can be selected. reloading timer ? 16-bit timer : 2 channels ? internal clock : 2 clock cycle resolutions, 2, 8 or 32 cycles can be selected. ? pin input : event counter input / gate function ? rectangular wave output other interval timer ? watchdog timer : 1 channel bit search module ? searches the first 1 / 0 change bit positions within 1 cycle from msb in 1 word. interruption controller ? external interruption input : mask impossible interruption (nmi ) , normal interruption 8 (int0 to int7) ? internal interruption factors : uart, dmac, a/d, reloading timer, ppg timer, delay interruption ? priority levels are programmable except for mask impossible interruption (16 levels) reset factors ? power-on reset / hardware standby / watchdog timer / software reset / external reset low power consumption mode ? sleep / stop mode clock control ? gear functions : operating clock frequencies peripheral to the cpu can be set randomly and independently. gear locks can be selected from 1/1, 1/2, 1/4 or 1/8 (or 1/2, 1/4, 1/8, or 1/16) . others ? package : lqfp-144 ? cmos technology : 0.35 m m ? power : 5.0 v 10 % , 3.3 v 5 %
MB91110 series 4 n n n n product lineup mb91v110 (for evaluation) MB91110 (i-ram mounted version) i-ram 16 kbyte 16 kbyte ram 5 kbyte 5 kbyte rom ?? i-$ 1 kbyte 1 kbyte dsu3 evaluation function mounted ?
MB91110 series 5 n n n n pin assignment (top view) (fpt-144p-m08) pe3/trg2, 5 pf0/int0 pf1/int1 pf2/int2 pf3/int3 pf4/int4 pf5/int5 pf6/int6 pf7/int7 v ss pg0/dreq0 pg1/dack0 pg2/deop0 pg3/dreq1 pg4/dack1 pg5/deop1 v cc 5 v cc 3 ph0/dreq2 ph1/dack2 ph2/deop2 ph3/si ph4/so ph5/sck ph6/ti0 ph7/to0 v ss pi0/ti1 pi1/to1 pi2/ppg0 pi3/ppg1 pi4/ppg2 pi5/ppg3 pi6/ppg4 pi7/ppg5 v ss nmi dw1/pb7 cs1h/pb6 cs1l/pb5 ras1/pb4 v ss v cc 5 dw0/pb3 cs0h/pb2 cs0l/pb1 ras0/pb0 clk/pa6 cs5/pa5 cs4/pa4 cs3/pa3 cs2/pa2 cs1/pa1 cs0 v ss wr1/p85 wr0 rd brq/p82 bgrnt/p81 rdy/p80 v cc 3 v cc 5 a23/p67 a22/p66 a21/p65 a20/p64 a19/p63 a18/p62 a17/p61 a16/p60 v ss 110 115 120 125 130 135 140 trg1, 4/pe2 trg0, 3/pe1 atg/pe0 v ss v cc 5 an7 an6 an5 an4 an3 an2 an1 an0 av ss avrl avrh av cc (open) (open) (open) (open) (open) (open) (open) (open) (open) v cc 3 hst rst v ss x1 x0 v cc 5 md2 md1 md0 p20/d16 p21/d17 p22/d18 p23/d19 p24/d20 p25/d21 p26/d22 p27/d23 v ss d24 d25 d26 d27 d28 d29 d30 d31 v cc 5 v ss a00 a01 a02 a03 a04 a05 a06 a07 v ss a08 a09 a10 a11 a12 a13 a14 a15 1 5 10 15 20 25 30 35 105 100 95 90 85 80 75 70 65 60 55 50 45 40 index
MB91110 series 6 n n n n pin descriptions (continued) pin no. pin name i/o* circuit type function 1 2 3 4 5 6 7 8 d16/p20 d17/p21 d18/p22 d19/p23 d20/p24 d21/p25 d22/p26 d23/p27 i/o c these pins use bits 16 to 23 of the external data bus. they can be used as a port (p20 to p27) if the external bus width is 8 bits. 10 11 12 13 14 15 16 17 d24 d25 d26 d27 d28 d29 d30 d31 i/o c these pins use bits 24 to 31 of the external data bus. 20 21 22 23 24 25 26 27 a00 a01 a02 a03 a04 a05 a06 a07 i/o c these pins use bits 00 to 07 of the external address bus. 29 30 31 32 33 34 35 36 a08 a09 a10 a11 a12 a13 a14 a15 i/o c these pins use bits 08 to 15 of the external address bus. 38 39 40 41 42 43 44 45 a16/p60 a17/p61 a18/p62 a19/p63 a20/p64 a21/p65 a22/p66 a23/p67 i/o c these pins use bits 16 to 23 of the external address bus. 48 rdy/p80 i/o c this is for external ready input. 0 is input if the bus cycle be- ing executed is incomplete. it can be used as a port when not otherwise used. 49 bgrnt /p81 i/o h this is the external bus open reception output. l is output if the external bus is opened. it can be used as a port when not otherwise used.
MB91110 series 7 (continued) pin no. pin name i/o* circuit type function 50 brq/p82 i/o c this is the external bus open request input. 1 is input if the external bus is to be opened. it can be used as a port when not otherwise used. 51 rd o g this is the external bus read strobe. 52 wr0 o g this is the external bus write strobe. 53 wr1 /p85 i/o h 55 cs0 o g chip select 0 output (low active) 56 57 58 59 60 cs1 /pa1 cs2 /pa2 cs3 /pa3 cs4 /pa4 cs5 /pa5 i/o h chip select 1 output (low active) chip select 2 output (low active) chip select 3 output (low active) chip select 4 output (low active) chip select 5 output (low active) they can be used as ports when not otherwise used. 61 clk/pa6 i/o h this is the system clock output. the same clock as the stan- dard clock is output. this can be used as a port when not oth- erwise used. 62 63 64 65 68 69 70 71 ras0/pb0 cs0l/pb1 cs0h/pb2 dw0 /pb3 ras1/pb4 cs1l/pb5 cs1h/pb6 dw1 /pb7 i/o h ras output with dram bank 0. casl output with dram bank 0. cash output with dram bank 0. we output with dram bank 0. (low active) ras output with dram bank 1. casl output with dram bank 1. cash output with dram bank 1. we output with dram bank 1. (low active) they can be used as ports when not otherwise used. 72 nmi i e non maskable interrupt (nmi) input. (low active) 73 74 75 md0 md1 md2 ii these are mode pins from 0 to 2. basic mcu operation modes are set using these pins. they should be connected directly to v cc or v ss for use. 77 78 x0 x1 i o a clock (oscillation) input. clock (oscillation) output. 80 rst i b this is the external reset input. (low active) 81 hst i e this is the hardware standby input. (low active) 83 (open) ?? set this to open. 84 85 86 (open) (open) (open) ?? set this to open. 16-bit bus width 8-bit bus width d31-24 wr0 wr0 d23-16 wr1 (port is possible)
MB91110 series 8 (continued) pin no. pin name i/o* circuit type function 87 88 89 90 (open) (open) (open) (open) ?? set this to open. 91 (open) ?? set this to open. 92 av cc ?? v cc power supply for the a/d converter. 93 avrh ?? a/d converter reference voltage (high potential side). be sure to turn on/off this pin with potential higher than avrh applied to v cc . 94 avrl ?? a/d converter reference voltage (low potential side). 95 av ss ?? v ss power supply for the a/d converter. 96 97 98 99 100 101 102 103 an0 an1 an2 an3 an4 an5 an6 an7 i d [an0 to 7] a/d converter analog input. 106 atg /pe0 i/o h [atg ] this is the external trigger input for the a/d converter. this function is always used if selected as the initiation factor for a/d, so output by other functions should be stopped ex- cept when it is carried out intentionally. [pe0] this is a general-purpose input/output port. 107 108 109 trg0, 3/pe1 trg1, 4/pe2 trg2, 5/pe3 i/o h [trg0 to 5] these are external trigger input pins of the ppg. [pe1 to 3] these are general-purpose input/output ports. 110 111 112 113 114 115 116 117 int0/pf0 int1/pf1 int2/pf2 int3/pf3 int4/pf4 int5/pf5 int6/pf6 int7/pf7 i/o f [int0 to 7] these are external interruption request inputs. this input is always used while the corresponding external interruption is permitted, so output using other functions should be stopped except when carried out intentionally. [pf0 to 7] these are general-purpose input/output ports. 119 dreq0/pg0 i/o h [dreq0] this is the dma external transfer request input (ch 0) . this input is always used if selected as the transfer factor for dmac, so outputs from other functions should be stopped except when carried out intentionally. [pg0] this is a multi-purpose input/output port.
MB91110 series 9 (continued) pin no. pin name i/o* circuit type function 120 dack0/pg1 i/o c [dack0] this is the dmac external transfer request recep- tion output (ch 0) . this function is effective if the transfer re- quest reception output specification of dmac is permitted. [pg1] this is a multi-purpose input/output port. this function is effective if the transfer request reception output specifica- tion of dmac is prohibited. 121 deop0/pg2 i/o c [deop0] this is the dma transfer end signal output (ch 0) . this function is effective if the transfer end signal output specification of dmac is permitted. [pg2] this is a multi-purpose input/output port. this function is effective if the transfer end signal output specification of dmac is prohibited. 122 dreq1/pg3 i/o h [dreq1] this is the dma external transfer request input (ch 1) . this input is always used if selected as the transfer factor of dmac, so output using other functions should be stopped except when carried out intentionally. [pg3] this is a multi-purpose input/output port. 123 dack1/pg4 i/o c [dack1] this is the dmac external transfer request recep- tion output (ch 1) . this function is effective if the transfer re- quest reception output specification of dmac is permitted. [pg4] this is a multi-purpose input/output port. this function is effective if the transfer request reception output specifica- tion of dmac is prohibited. 124 deop1/pg5 i/o c [deop1] this is the dma transfer end signal output (ch 1) . this function is effective if the transfer end signal output specification of dmac is permitted. [pg5] this is a multi-purpose input/output port. this function is effective if the transfer end signal output specification of dmac is prohibited. 127 dreq2/ph0 i/o h [dreq2] this is the dma external transfer request input (ch 2) . this input is always used if selected as the transfer factor of dmac, so output using other functions should be stopped except when carried out intentionally. [ph0] this is a multi-purpose input/output port. 128 dack2/ph1 i/o c [dack2] this is the dmac external transfer request recep- tion output (ch 2) . this function is effective if the transfer re- quest reception output specification of dmac is permitted. [ph1] this is a multi-purpose input/output port. this function is effective if the transfer request reception output specifica- tion of dmac is prohibited.
MB91110 series 10 (continued) pin no. pin name i/o* circuit type function 129 deop2/ph2 i/o c [deop2] this is the dma transfer end signal output (ch 2) . this function is effective if the transfer end signal output specification of dmac is permitted. [ph2] this is a multi-purpose input/output port. this function is effective if the transfer end signal output specification of dmac is prohibited. 130 si/ph3 i/o h [si] this is uart data input. this input is always used while uart inputs, so outputs from other functions should be stopped except when carried out intentionally. [ph3] this is a general-purpose input/output port. 131 so/ph4 i/o c [so] this is uart data output. this function is effective when uart data output specification is permitted. [ph4] this is a general-purpose input/output port. this func- tion is effective when uart data output specification is pro- hibited. 132 sck/ph5 i/o h [sck] this is uart clock input/output. clock output is effec- tive when uart clock output specification is permitted. [ph5] this is a general-purpose input/output port. this func- tion is effective when uart clock output specification is pro- hibited. 133 ti0/ph6 i/o h [ti0] this is reload timer 0 input. it is always used when re- load timer input is permitted, so outputs from other functions should be stopped except when carried out intentionally. [ph6] this is a general-purpose input/output port. 134 to0/ph7 i/o c [to0] this is reload timer 0 output. this function is effective when reload timer specification is permitted. [ph7] this is a general-purpose input/output port. this func- tion is effective when reload timer specification is prohibited. 136 ti1/pi0 i/o h [ti1] this is reload timer 1 input. it is always used when re- load timer input is permitted, so outputs from other functions should be stopped except when carried out intentionally. [pi0] this is a general-purpose input/output port. 137 to1/pi1 i/o c [t01] this is the reload timer 1 output. this function is effec- tive if the output specification of the reload timer is permitted. [pi1] this is a multi-purpose input/output port. this function is effective if the output specification of the reload timer is prohibited.
MB91110 series 11 (continued) * : i/o shown above indicates input/output classification. note : the i/o port and resource input/outputs for most of the above pins are multiplexed, i.e. pxx/xxxx. in the event of both the port and resource outputs were to use the same pins, the resource is given priority. pin no. pin name i/o* circuit type function 138 139 140 141 142 143 ppg0/pi2 ppg1/pi3 ppg2/pi4 ppg3/pi5 ppg4/pi6 ppg5/pi7 i/o c [ppg0 to 5] this is the ppg timer 1 output. this function is effective if the output specification of the ppg timer is permit- ted. [pi2 to 7] this is a multi-purpose input/output port. this func- tion is effective if the output specification of the ppg timer is prohibited. 18 46 66 76 104 125 v cc 5 ?? this provides power for the 5 v digital circuit system. 47 82 126 v cc 3 ?? this provides power for the 3 v digital circuit system. 9 19 28 37 54 67 79 105 118 135 144 v ss ?? this is the earth level for digital circuits.
MB91110 series 12 n n n n i/o circuit type (continued) type circuit types remarks a ? oscillation feedback resistance : approximately 1 m w ? 12.5 mhz oscillation b ? cmos level hysteresis input without standby control with pull-up resistance c ? cmos level output cmos level input with standby control d ? a/d converter analog input pin x1 standby control x0 clock input v ss v cc p-channel type tr digital input standby control digital output digital output digital input analog input
MB91110 series 13 (continued) type circuit types remarks e ? cmos level hysteresis input without standby control f ? cmos level output ? cmos level hysteresis input without standby control g ? cmos level output h ? cmos level output ? cmos level hysteresis input with standby control i ? cmos level input without standby control digital input digital output digital output digital input digital output digital output standby control digital output digital output digital input digital input
MB91110 series 14 n n n n handling devices ? preventing latch-up the latch-up phenomenon may be generated if a voltage in excess of v cc or lower than v ss is applied to the input/output pins, or if the voltage exceeds the rating between v cc and v ss . if latch-up is generated, the electrical current increases significantly and may destroy certain components due to the excessive heat, so great care must be taken to ensure that the maximum rating is not exceeded during use. ? handling unused input pins input pins that are not used should be pulled up or down as they may cause erroneous operations if they are left open. ? external reset input l level should be input to the rst pin, which is required for at least five machine cycles to ensure the internal status is reset. ? using external clocks if external clock is used, x0 pin should be provided, and x1 pin should be provided with reverse phase to x0 pin input. if the stop mode (oscillation stop mode) is used simultaneously, the x1 pin is stopped with the h output. so, when stop mode is specified, approximately 1 k w of resistance should be added externally. an example of the external clock usage methods is shown in the following circuit. note : resistance must be added to the x1 pin if the stop mode (oscillation stop mode) is used. ? power supply pins in products with multiple vcc or vss pins, the pins of the same potential are internally connected in the device to avoid abnormal operations including latch-up. however you must connect the pins to an external power and a ground line to lower the electro-magnetic emission level to prevent abnormal operation of strobe signals caused by the rise in the ground level, and to conform to the total current rating. make sure to connect vcc and vss pins via the lowest impedance to power lines. it is recommended to provide a bypass capacitor of around 0.1 f between vcc and vss pins near the device. ? crystal oscillator circuits noise around the x0 or x1 pins may cause erroneous operation. make sure to provide bypass capacitors via shortest distances from x0, x1 pins, crystal oscillator (or ceramic resonator) and ground lines, and make sure that lines of oscillation circuits not cross the lines of other circuit. a printed circuit board artwork surrounding the x0 and x1 pins with ground area for stabilizing the operation is highly recommended . x0 x1 MB91110 example of external clock usage (normal case)
MB91110 series 15 ? n.c. pins n.c. pins must be opened for use. ? mode pins (md0 to md2) those pins must be directly connected to v cc or v ss for use. pattern length between v cc or v ss and each mode pin on the printed-circuit board should be arranged to be as short as possible to prevent the test mode being erroneously turned on due to noise, they should also be connected with low impedance. ? in the event that power is turned on the rst pin must be started from l level when the power is turned on, and when the power is adjusted to the v cc level it should be changed to the h level after being left for at least five cycles of the internal operation clock. ? original oscillation input in the event that power is turned on the clock must be input until the waiting status for oscillation stability is reset in the event that power is turned on. ? hardware standby in the event that power is turned on standby is not set in the event that power is turned on while the hst pin is set at l level. the hst pin becomes effective after being reset, but it must first be returned to h level. ? power on reset when power is turned on, power on reset must be executed. if the power voltage falls below the guaranteed operating voltage, power on reset must be executed by turning on power supply again. ? restrictions for standby programs to be set for stop and sleep must be placed on the rom in the c-bus or address area of the external memory. if placed in the rom address area on the i-bus, operation can not be guaranteed after returning. ? execution of programs in i-rom/ram areas in the event that programs in the i-rom/ram areas are executed, enter the i-rom/ram areas in accordance with the jmp system instruction. conversely, when accessing from programs in the i-rom/ram area to those in other areas, exit in accordance with the jmp system instructions.
MB91110 series 16 n n n n block diagram fr30 cpu d-bus (32 bit) harvard prinston bus converter bit search module dmac (5 ch) dreq0 dack0 deop0 dreq1 dack1 deop1 dreq2 dack2 deop2 32 bit 16 bit bus converter x0 x1 rst hst clock control unit int0 ~ int7 nmi interrupt control unit an0 ~ an7 atg av cc av ss avrh avrl ti0 ti1 to0 to1 a/d converter (8 ch) reload timer (2 ch) port e ~ i r-bus (16 bit) uart 16 bit ppg timer (6 ch) si so sck ppg0 ~ ppg5 trg0 ~ trg5 (32 bit) c-bus port 0 ~ b dram controller bus controller ras0 cs0l cs0h dw0 ras1 cs1l cs1h dw1 d31 ~ d16 a23 ~ a00 rd wr0 ~ wr 1 rdy clk cs0 ~ cs5 brq bgrnt ram pll 50 mhz 5 kb instruction ram instruction cache 1 kb 16 kb 50 mhz ? 25 mhz 50 mhz 25 mhz i-bus (16 bit) note : pins are described per function. some of the pins are multiplexed. in the event that realos is used, an external interruption or built-in timer should be used to control the time.
MB91110 series 17 n n n n memory space the fr30 series has 4 gbytes (2 32 addresses) of logic address space which the cpu accesses linearly. 1. memory map note : MB91110 series only supports internal rom external bus mode. ? direct addressing area the following areas of the address space are used for i/o. this area is called the direct addressing area and the address of the operand can be specified directly during instruction. the direct area differs depending on data size to be accessed. byte data access : 0-0ff h half-word data access : 0-1ff h word data access : 0-3ff h 0000 0000 h 0000 0400 h 0000 0800 h 0000 1000 h 0000 2400 h 0001 0000 h 0008 0000 h 000b c000 h 000c 0000 h 0010 0000 h ffff ffff h i/o i/o i-ram/rom 16 kb internal rom external bus modes access is prohibited built-in ram 5 kb access is prohibited access is prohibited external area external area external area direct addressing area (refer to "i/o map") operating as the internal rom. reading mode only can be accessed in the case of i-ram.
MB91110 series 18 2. registers there are two types of multi-purpose registers in the fr family. one is a dedicated purpose register that exists within the cpu and the other is a multi-purpose register that exists in the memory. ? dedicated registers ? program status (ps) ps is the register that holds the program status and is classified into three categories, namely, condition code register (ccr) , system condition code register (scr) and interruption level master register (ilm) . program counter (pc) : 32-bit length; indicates instruction storage position. program status (ps) : 32-bit length; stores register pointers and condition codes. table base register (tbr) : holds the starting address of the vector table to be used for exception, in- terruption and trapping (eit) . return pointer (rp) : holds the address to which you will return to from the sub-routine. system stuck pointer (ssp) : indicates the systems stuck position. user stuck pointer (usp) : indicates the users stuck position. multiplication and division results resister (mdh/mdl) : 32-bit length; these are the registers for multiplication and division. pc ps tbr rp ssp usp mdh mdl xxxx xxxx h (undecided) xxxx xxxx h (undecided) xxxx xxxx h (undecided) xxxx xxxx h (undecided) xxxx xxxx h (undecided) 0000 0000 h 000f fc00 h 32 bit program counter program status table base register return pointer system stuck pointer user stuck pointer multiplication and division results resister initial values ps ilm4 ilm3 ilm2 ilm scr ccr ilm1 ilm0 d1 d0 t s i n z v c 0 1 2 3 4 5 6 7 8 9 10 16 17 18 19 20 31 to 21 ???? 15 to 11
MB91110 series 19 ? condition code register (ccr) ? system condition code register (scr) ? interruption level mask register (ilm) s flag : specifies the stuck pointer to be used as r15. i flag : controls permission and prohibition of user interruption requests. n flag : indicates codes when the computation results are defined as integers that are expressed in complements of 2. z flag : indicates if arithmetic results were 0. v flag : indicates when operands are used for computation and defined as integers expressed in com- plements of 2, and indicates whether or not an overflow is generated as a result of the compu- tation. c flag : indicates whether carrying or borrowing is generated from the highest bit as a result of the com- putation. t flag : specifies whether or not the step- trace- trap will be valid. ilm4 to ilm0 : holds the interruption level mask values, and those values that are held by the ilm are used for the level mask. interruption requests can only be accepted when the interruption levels handled within the interruption requests to be input into the cpu are stronger than the levels shown by the ilm. ilm4 ilm3 ilm2 ilm1 ilm0 interruption level strength 00000 0 strong 01000 15 11111 31 weak
MB91110 series 20 n n n n multi-purpose registers the multi-purpose registers are cpu registers (r0 to r15) which are used as accumulators for various compu- tations and memory access pointers (field that indicates the address) . special purposes are assumed for the following three registers out of the 16 registers. thus, some instructions are emphasized. r13 : virtual accumulator (ac) r14 : frame pointer (fp) r15 : stack pointer (sp) initial values for r0 to r14 on resetting are unspecified. the initial value of r15 will be 0000 0000 h (ssp value) . ? register bank configuration r0 r1 r12 r13 r14 r15 ac (accumulator) fp (frame pointer) sp (stack pointer) xxxx xxxx h xxxx xxxx h 0000 0000 h 32-bit initial value
MB91110 series 21 n n n n mode setting 1. pins ? mode pins and set mode * : MB91110 series is not supported single chip mode. 2. register ? mode register (modr) and set mode ? bus mode set bit and its functions mode pins mode name reset vector access areas external data bus width bus modes md2 md1 md0 000 external vector mode 0 external 8-bit external rom external bus mode 001 external vector mode 1 external 16-bit 010 ??? setting is prohibited 011 internal vector mode internal (mode register) single chip mode* 1 ????? usage is prohibited m1 m0 functions remarks 0 0 single chip mode not supported 0 1 internal rom external bus mode 1 0 external rom external bus mode 11 ? setting is prohibited address initial value access 0000 07ff h xxxxxxxx b w m1 m0 ****** bus mode set bit w : write only x : undecided * : 0 should always be written for bits other than m1 and m0.
MB91110 series 22 n n n n i/o map (continued) address register internal resource + 0 + 1 + 2 + 3 000000 h ? pdr2 (r/w) ?? port data register xxxxxxxx 000004 h ? pdr6 (r/w) ?? xxxxxxxx 000008 h pdrb (r/w) pdra (r/w) ? pdr8 (r/w) xxxxxxxx - xxxxxx -- - x - - xxx 00000c h ? 000010 h ?? pdre (r/w) pdrf (r/w) - - - - xxxx xxxxxxxx 000014 h pdrg (r/w) pdrh (r/w) pdri (r/w) ? - - xxxxxx xxxxxxxx xxxxxxxx 000018 h ? reserved 00001c h ? reserved 000020 h ssr (r/w) sidr/sodr (r/w) scr (r/w) smr (r/w) uart 0 0 0 0 1 - 0 0 xxxxxxxx 0 0 0 0 0 1 0 00 0 0 0 0 - 0 0 000024 h ? cdcr (r/w) ? 0 - - 1 1 1 1 1 000028 h tmrlr (w) tmr (r) reload timer 0 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00002c h ? tmcsr (r/w) - - - - 0 0 0 00 0 0 0 0 0 0 0 000030 h tmrlr (w) tmr (r) reload timer 1 xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000034 h ? tmcsr (r/w) - - - - 0 0 0 00 0 0 0 0 0 0 0 000038 h adcr (r) adcs (r/w) a/d converter (sequential comparison type) - - - - - - xx xxxxxxxx 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 00003c h ? reserved
MB91110 series 23 (continued) address register internal resource + 0 + 1 + 2 + 3 000040 h ? reserved 000044 h access is prohibited pcsr (w) ppg0 xxxxxxxx xxxxxxxx 000048 h pdut (w) pcnh (r/w) pcnl (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 00004c h access is prohibited pcsr (w) ppg1 xxxxxxxx xxxxxxxx 000050 h pdut (w) pcnh (r/w) pcnl (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 000054 h access is prohibited pcsr (w) ppg2 xxxxxxxx xxxxxxxx 000058 h pdut (w) pcnh (r/w) pcnl (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 00005c h access is prohibited pcsr (w) ppg3 xxxxxxxx xxxxxxxx 000060 h pdut (w) pcnh (r/w) pcnl (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 000064 h access is prohibited pcsr (w) ppg4 xxxxxxxx xxxxxxxx 000068 h pdut (w) pcnh (r/w) pcnl (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 00006c h access is prohibited pcsr (w) ppg5 xxxxxxxx xxxxxxxx 000070 h pdut (w) pcnh (r/w) pcnl (r/w) xxxxxxxx xxxxxxxx 0 0 0 0 0 0 0 -0 0 0 0 0 0 0 0 000074 h ? reserved 000078 h ? 00007c h ? 000080 h ?
MB91110 series 24 (continued) address register internal resource + 0 + 1 + 2 + 3 000084 h ? reserved 000088 h ? 00008c h ? 000090 h ? 000094 h eirr (r/w) enir (r/w) ? external interruption/ nmi 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000098 h elvr (r/w) ? 0 0 0 0 0 0 0 00 0 0 0 0 0 0 0 00009c h ? reserved 0000a0 h ? 0000a4 h ? 0000a8 h ? 0000ac h ? 0000b0 h ? 0000b4 h ? 0000b8 h ? 0000bc h ? 0000c0 h ? 0000c4 h ?
MB91110 series 25 (continued) address register internal resource + 0 + 1 + 2 + 3 0000c8 h ? reserved 0000cc h ? 0000d0 h ?? ddre (w) ddrf (w) data direction register - - - - 0 0 0 00 0 0 0 0 0 0 0 0000d4 h ddrg (w) ddrh (w) ddri (w) ? - - 0 0 0 0 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 0000d8 h to 0000fc h ? reserved 000100 h to 0001fc h ? reserved 000200 h dmacs0 (r/w) dma controller channel 0 0 - 0 0 - 0 0 00 0 - - 0 0 0 0xx - 0 0 0 0 0- - - - xx - x 000204 h dmacc0 (r/w) - - - - xxxx xxxx - xxx xxxxxxxx xxxxxxxx 000208 h dmasa0 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00020c h dmada0 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000210 h dmacs1 (r/w) dma controller channel 1 0 - 0 0 - 0 0 00 0 - - 0 0 0 0xx - 0 0 0 0 0- - - - xx - x 000214 h dmacc1 (r/w) - - - - xxxx xxxx - xxx xxxxxxxx xxxxxxxx 000218 h dmasa1 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00021c h dmada1 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx
MB91110 series 26 (continued) address register internal resource + 0 + 1 + 2 + 3 000220 h dmacs2 (r/w) dma controller channel 2 0 - 0 0 - 0 0 00 0 - - 0 0 0 0xx - 0 0 0 0 0- - - - xx - x 000224 h dmacc2 (r/w) - - - - xxxx xxxx - xxx xxxxxxxx xxxxxxxx 000228 h dmasa2 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00022c h dmada2 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000230 h dmacs3 (r/w) dma controller channel 3 0 - 0 0 - 0 0 00 0 - - 0 0 0 0xx - 0 0 0 0 0- - - - xx - x 000234 h dmacc3 (r/w) - - - - xxxx xxxx - xxx xxxxxxxx xxxxxxxx 000238 h dmasa3 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00023c h dmada3 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000240 h dmacs4 (r/w) dma controller channel 4 0 - 0 0 - 0 0 00 0 - - 0 0 0 0xx - 0 0 0 0 0- - - - xx - x 000244 h dmacc4 (r/w) - - - - xxxx xxxx - xxx xxxxxxxx xxxxxxxx 000248 h dmasa4 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 00024c h dmada4 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000250 h dmacr (r/w) overall dma controller - - - - - - - - - - - - - - - - 0 0 - - - - - - - - - - - - - 0 000254 h ? reserved 000258 h ? 00025c h ? 000260 h ?
MB91110 series 27 (continued) address register internal resource + 0 + 1 + 2 + 3 000264 h ? reserved 000268 h ? 00026c h ? 000270 h ? 000274 h ? 000278 h to 0002fc h ? 000300 h to 0003e0 h ? 0003e4 h ? ichcr (r/w) instruction cache - - 0 0 0 0 0 0 0003e8 h ? reserved 0003ec h ? irmc (r/w) i-ram control - - - - - - - 0 0003f0 h bsd0 (w) bit search module xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f4 h bsd1 (r/w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003f8 h bsdc (w) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 0003fc h bsrr (r) xxxxxxxx xxxxxxxx xxxxxxxx xxxxxxxx 000400 h icr00 (r/w) icr01 (r/w) icr02 (r/w) icr03 (r/w) interruption controller - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 000404 h icr04 (r/w) icr05 (r/w) icr06 (r/w) icr07 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1
MB91110 series 28 (continued) address register internal resource + 0 + 1 + 2 + 3 000408 h icr08 (r/w) icr09 (r/w) icr10 (r/w) icr11 (r/w) interruption controller - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 00040c h icr12 (r/w) icr13 (r/w) icr14 (r/w) icr15 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 000410 h icr16 (r/w) icr17 (r/w) icr18 (r/w) icr19 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 000414 h icr20 (r/w) icr21 (r/w) icr22 (r/w) icr23 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 000418 h icr24 (r/w) icr25 (r/w) icr26 (r/w) icr27 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 00041c h icr28 (r/w) icr29 (r/w) icr30 (r/w) icr31 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 000420 h icr32 (r/w) icr33 (r/w) icr34 (r/w) icr35 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 000424 h icr36 (r/w) icr37 (r/w) icr38 (r/w) icr39 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 000428 h icr40 (r/w) icr41 (r/w) icr42 (r/w) icr43 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 00042c h icr44 (r/w) icr45 (r/w) icr46 (r/w) icr47 (r/w) - - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1- - - 1 1 1 1 1 000430 h dicr (r/w) hrcl (r/w) ?? delay interruption - - - - - - - 0- - - 1 1 1 1 1 000434 h to 00047c h ? reserved 000480 h rsrr/wtcr (r/w) stcr (r/w) pdrr (r/w) ctbr (w) clock control area 1 xxxx - 0 0 0 0 0 1 1 1 - -- - - - 0 0 0 0 xxxxxxxx 000484 h gcr (r/w) wpr (w) ? 1 1 0 0 1 1 - 1 xxxxxxxx 000488 h pctr (r/w) ? pll control register 0 0 - - 0 - - - 00048c h to 0005fc h ? reserved
MB91110 series 29 (continued) note : do not execute rmw instructions to registers with write-only bits. rmw instruction (rmw : read / modify / write) data in areas with ? or reserved ones is undecided. address register internal resource + 0 + 1 + 2 + 3 000600 h ? ddr2 (w) ?? data direction register 0 0 0 0 0 0 0 0 000604 h ? ddr6 (w) ?? 0 0 0 0 0 0 0 0 000608 h ddrb (w) ddra (w) ? ddr8 (w) 0 0 0 0 0 0 0 0- 0 0 0 0 0 0 -- - 0 - - 0 0 0 00060c h asr1 (w) amr1 (w) external bus interface 0 0 0 0 0 0 0 00 0 0 0 0 0 0 10 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000610 h asr2 (w) amr2 (w) 0 0 0 0 0 0 0 00 0 0 0 0 0 1 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000614 h asr3 (w) amr3 (w) 0 0 0 0 0 0 0 00 0 0 0 0 0 1 10 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000618 h asr4 (w) amr4 (w) 0 0 0 0 0 0 0 00 0 0 0 0 1 0 00 0 0 0 0 0 0 00 0 0 0 0 0 0 0 00061c h asr5 (w) amr5 (w) 0 0 0 0 0 0 0 00 0 0 0 0 1 0 10 0 0 0 0 0 0 00 0 0 0 0 0 0 0 000620 h amd0 (r/w) amd1 (r/w) amd32 (r/w) amd4 (r/w) - - - 0 0 1 1 10 - - 0 0 0 0 00 0 0 0 0 0 0 00 - - 0 0 0 0 0 000624 h amd5 (r/w) dscr (w) rfcr (r/w) 0 - - 0 0 0 0 00 0 0 0 0 0 0 0- - xxxxxx 0 - - - 0 0 0 0 000628 h epcr0 (w) epcr1 (w) - - - - 1 1 0 0- 1 1 1 1 1 1 1 - - - - - - - - 1 1 1 1 1 1 1 1 00062c h dmcr4 (r/w) dmcr5 (r/w) 0 0 0 0 0 0 0 00 0 0 0 0 0 0 -0 0 0 0 0 0 0 00 0 0 0 0 0 0 - 000630 h to 0007f8 h ? reserved 0007fc h ? ler (w) modr (w) little endian register mode register - - - - - 0 0 0 xxxxxxxx and rj, @ri or rj, @ri eor rj, @ri andh rj, @ri orh rj, @ri eorh rj, @ri andb rj, @ri orb rj, @ri eorb rj, @ri bandl #u4, @ri borl #u4, @ri beorl #u4, @ri bandh #u4, @ri borh #u4, @ri beorh #u4, @ri
MB91110 series 30 n n n n interruption vector interruption factor and allocation of interruption vectors / interruption control registers are described in the interruption vector table. (continued) interruption source interruption number interruption level *1 offset interruption vector address to tbr of default *2 decimal hexadeci- mal reset 0 00 ? 3fc h 000ffffc h system reservation 1 01 ? 3f8 h 000ffff8 h system reservation 2 02 ? 3f4 h 000ffff4 h system reservation 3 03 ? 3f0 h 000ffff0 h system reservation 4 04 ? 3ec h 000fffec h system reservation 5 05 ? 3e8 h 000fffe8 h system reservation 6 06 ? 3e4 h 000fffe4 h coprocessor absence trap 7 07 ? 3e0 h 000fffe0 h coprocessor error trap 8 08 ? 3dc h 000fffdc h inte instruction 9 09 4 fixed 3d8 h 000fffd8 h system reservation 10 0a ? 3d4 h 000fffd4 h system reservation 11 0b ? 3d0 h 000fffd0 h step trace trap 12 0c 4 fixed 3cc h 000fffcc h system reservation 13 0d ? 3c8 h 000fffc8 h exceptions to undefined instructions 14 0e ? 3c4 h 000fffc4 h nmi request 15 0f 15 (f h ) fixed 3c0 h 000fffc0 h system reservation 16 10 icr00 3bc h 000fffbc h system reservation 17 11 icr01 3b8 h 000fffb8 h external interruption 0 18 12 icr02 3b4 h 000fffb4 h external interruption 1 19 13 icr03 3b0 h 000fffb0 h external interruption 2 20 14 icr04 3ac h 000fffac h external interruption 3 21 15 icr05 3a8 h 000fffa8 h external interruption 4 22 16 icr06 3a4 h 000fffa4 h external interruption 5 23 17 icr07 3a0 h 000fffa0 h external interruption 6 24 18 icr08 39c h 000fff9c h external interruption 7 25 19 icr09 398 h 000fff98 h system reservation 26 1a icr10 394 h 000fff94 h uart reception completion 27 1b icr11 390 h 000fff90 h system reservation 28 1c icr12 38c h 000fff8c h system reservation 29 1d icr13 388 h 000fff88 h uart transmission completion 30 1e icr14 384 h 000fff84 h system reservation 31 1f icr15 380 h 000fff80 h
MB91110 series 31 (continued) interruption source interruption number interruption level *1 offset interruption vector address to tbr of default *2 decimal hexadeci- mal system reservation 32 20 icr16 37c h 000fff7c h dmac0 (end, error) 33 21 icr17 378 h 000fff78 h dmac1 (end, error) 34 22 icr18 374 h 000fff74 h dmac2 (end, error) 35 23 icr19 370 h 000fff70 h dmac3 (end, error) 36 24 icr20 36c h 000fff6c h dmac4 (end, error) 37 25 icr21 368 h 000fff68 h system reservation 38 26 icr22 364 h 000fff64 h system reservation 39 27 icr23 360 h 000fff60 h system reservation 40 28 icr24 35c h 000fff5c h a/d sequential conversion type 41 29 icr25 358 h 000fff58 h reload timer 0 42 2a icr26 354 h 000fff54 h reload timer 1 43 2b icr27 350 h 000fff50 h 16-bit ppg timer 0 44 2c icr28 34c h 000fff4c h 16-bit ppg timer 1 45 2d icr29 348 h 000fff48 h 16-bit ppg timer 2 46 2e icr30 344 h 000fff44 h 16-bit ppg timer 3 47 2f icr31 340 h 000fff40 h 16-bit ppg timer 4 48 30 icr32 33c h 000fff3c h 16-bit ppg timer 5 49 31 icr33 338 h 000fff38 h system reservation 50 32 icr34 334 h 000fff34 h system reservation 51 33 icr35 330 h 000fff30 h system reservation 52 34 icr36 32c h 000fff2c h system reservation 53 35 icr37 328 h 000fff28 h system reservation 54 36 icr38 324 h 000fff24 h system reservation 55 37 icr39 320 h 000fff20 h system reservation 56 38 icr40 31c h 000fff1c h system reservation 57 39 icr41 318 h 000fff18 h system reservation 58 3a icr42 314 h 000fff14 system reservation 59 3b icr43 310 h 000fff10 h system reservation 60 3c icr44 30c h 000fff0c h system reservation 61 3d icr45 308 h 000fff08 h system reservation 62 3e icr46 304 h 000fff04 h delay interruption factor bit 63 3f icr47 300 h 000fff00 h system reservation (used under realos) *3 64 40 ? 2fc h 000ffefc h
MB91110 series 32 (continued) *1 : icr sets the interruption level for each interruption request using the register built into the interruption controller. icr is prepared in accordance with each interruption request. *2 : tbr is the register that indicates the starting address of the vector table for eit. addresses with added offset values that are specified per tbr and eit factor will be the vector addresses. *3 : realos os/fr uses 0x40, 0x41 interruptions for system codes. reference : the vector area for eit is 1 kb in accordance with the address shown by tbr. the size per vector is 4 bytes, and the relationship between the vector numbers and their addresses is shown as follows. interruption source interruption number interruption level *1 offset interruption vector address to tbr of default *2 decimal hexadeci- mal system reservation (used under realos) *3 65 41 ? 2f8 h 000ffef8 h used under int instruction 66 to 255 42 to ff ? 2f4 h to 000 h 000ffef4 h to 000ffd00 h vctadr = tbr + vctofs = tbr + (3fc h - 4 vct) vctadr : vector address vctofs : vector offset vct : vector number
MB91110 series 33 n n n n peripheral resources 1. i/o port MB91110 series can be used as the i/o port when settings for resources that handle each pin do not to use the pins for input/output. ? block diagram ? i/o port registers i/o port is composed of the port data register (pdr) and data direction register (ddr) . in cases where the input mode is ddr = 0 for pdr reading : level of external pins to be handled is read out. for pdr writing : set value is written in pdr. in cases where the output mode is ddr = 1 for pdr reading : pdr value is read out. for pdr writing : set value is written in pdr and the pdr value is simultaneously output to the externally handled pin. pdr ddr 1 0 1 0 data bus pin pdr read pdr : port data register ddr : data direction register resource input resource output resource output allowed
MB91110 series 34 2. port data register (pdr) port data register (pdr2-i) is the input/output data register for the i/o port. input/output control is carried out by the handled data direction register (ddr2-i) . ? port data register (pdr) pdr2 initial value access address : 000001 h xxxxxxxx b r/w pdr6 initial value access address : 000005 h xxxxxxxx b r/w pdr8 initial value access address : 00000b h - - x- - xxx b r/w pdra initial value access address : 000009 h - xxxxxx- b r/w pdrb initial value access address : 000008 h xxxxxxxx b r/w pdre initial value access address : 000012 h - - - - xxxx b r/w pdrf initial value access address : 000013 h xxxxxxxx b r/w pdrg initial value access address : 000014 h - - xxxxxx b r/w pdrh initial value access address : 000015 h xxxxxxxx b r/w pdri initial value access address : 000016 h xxxxxxxx b r/w 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 ? ? p85 ?? p82 p81 p80 7654 321 0 pa6 ? pa5 pa4 pa3 pa2 pa1 ? 7654 321 0 pb6 pb7 pb5 pb4 pb3 pb2 pb1 pb0 7654 321 0 ? ??? pe3 pe2 pe1 pe0 7654 321 0 pf6 pf7 pf5 pf4 pf3 pf2 pf1 pf0 7654 321 0 ? ? pg5 pg4 pg3 pg2 pg1 pg0 7654 321 0 ph6 ph7 ph5 ph4 ph3 ph2 ph1 ph0 7654 321 0 pi6 pi7 pi5 pi4 pi3 pi2 pi1 pi0
MB91110 series 35 3. data direction register (ddr) the data direction register (ddr2-i) controls the input/output direction of the i/o port per bit. 0 is used for input and 1 is used to execute output control. ? data direction register (ddr) ddr2 initial value access address : 000601 h 00000000 b w ddr6 initial value access address : 000605 h 00000000 b w ddr8 initial value access address : 00060b h - - 0 - - 000 b w ddra initial value access address : 000609 h - 000000 - b w ddrb initial value access address : 000608 h 00000000 b w ddre initial value access address : 0000d2 h - - - - 0000 b w ddrf initial value access address : 0000d3 h 00000000 b w ddrg initial value access address : 0000d4 h - - 000000 b w ddrh initial value access address : 0000d5 h 00000000 b w ddri initial value access address : 0000d6 h 00000000 b w 7654 321 0 p26 p27 p25 p24 p23 p22 p21 p20 7654 321 0 p66 p67 p65 p64 p63 p62 p61 p60 7654 321 0 ? ? p85 ?? p82 p81 p80 7654 321 0 pa6 ? pa5 pa4 pa3 pa2 pa1 ? 7654 321 0 pb6 pb7 pb5 pb4 pb3 pb2 pb1 pb0 7654 321 0 ? ??? pe3 pe2 pe1 pe0 7654 321 0 pf6 pf7 pf5 pf4 pf3 pf2 pf1 pf0 7654 321 0 ? ? pg5 pg4 pg3 pg2 pg1 pg0 7654 321 0 ph6 ph7 ph5 ph4 ph3 ph2 ph1 ph0 7654 321 0 pi6 pi7 pi5 pi4 pi3 pi2 pi1 pi0
MB91110 series 36 4. instruction cache the instruction cache is a temporary storage memory. in the event that the instruction codes are accessed from a low speed external memory, it holds the accessed codes internally, and is used to increase the access speed for all subsequent accesses. direct read or write access can not be done by instruction cache or instruction cache tag using software. ? cacheable area of the instruction cache instruction cache allows all space to become a cacheable area. ? built-in rom shall also be cacheable for products featuring built-in roms. ? it is assumed that instruction access is not carried out to spaces other than external areas and built-in roms. thus, even if an instruction access is made, it would be cacheable to the control register in the i/o area. ? even though details of the external memory are updated by dma transfer, it is not coherent with the cache details. in this case, coherency should be established by flushing the cache. ? instruction cache configuration ? basic instruction length of fr series : 2 bytes ? block layout : 2-way set associative type ?block 1 way is configured of 32 blocks. 1 block is 16 bytes ( = 4 sub blocks) 1 sub block is 4 bytes ( = 1 bus access unit) the instruction cache configuration is shown in the following figure. 4 bytes 4 bytes 4 bytes 4 bytes 4 bytes i3 i2 i1 i0 way 1 way 2 cache tag sub lock 3 sub lock 2 sub lock 1 sub lock 0 block 0 sub lock 3 sub lock 2 sub lock 1 sub lock 0 block 31 block 0 block 31 sub lock 3 sub lock 2 sub lock 1 sub lock 0 sub lock 3 sub lock 2 sub lock 1 sub lock 0 cache tag cache tag cache tag 32 blocks 32 blocks instruction cache configuration
MB91110 series 37 5. instruction cache control register (ichcr) the instruction cache control register (ichcr) controls the operation of the instruction cache. writing to ichcr may effect the cache operation of instructions to be retrieved within the next three cycles. ? instruction cache control register (ichcr) instruction cache control register (ichcr) is shared for use by ways 1 and 2. initial value access address : 0000 03e7 h - - 000000 r/w 07 06 05 04 03 02 01 00 ? ? gblk alfl eolk elkr flsh enab global lock auto lock fail entry auto lock entry lock release flush enable
MB91110 series 38 6. clock generator (low power consumption mechanism) the clock generation area is a module with the following functions. ? cpu clock generation (including gear function) ? peripheral clock generation (including gear function) ? reset generation and holding factors ? standby function (including hardware standby) ? restraining dma request ? pll (phase locked loop) is built in ?register list address initial value access 000480 h 000481 h 1xxxx- 00 b 000111 - - b r/w r/w 000482 h 000483 h - - - - 0000 b xxxxxxxx b r/w w 000484 h 000485 h 110011- 1 b xxxxxxxx b r/w w 000488 h 00 - - 0 - - - b r/w stcr ctbr rsrr/wtcr pdrr wpr gcr pctr 07 06 05 04 03 02 01 00 15 14 13 12 11 10 09 08
MB91110 series 39 ? block diagram x0 x1 1/2 pll r | b u s [ gear control area ] gcr register pctr register cpu gear peripheral gear [ stop/sleep control area ] stcr register [ dma blocking circuit ] pdrr register [ reset factor circuit ] rsrr register [ watchdog control area ] wpp register ctbr register selection circuit internal clock generation circuit status transfer control circuit watchdog f/f time base timer oscilla- tion circuit internal interruption internal reset cpu hold permission hst pin dma request power on cell rst pin cpu clock internal bus clock external bus clock peripheral dma clock internal peripheral clock stop status sleep status cpu hold request internal reset reset generation f/f count clock
MB91110 series 40 7. bus interface outline the bus interface controls the interface with external memory and external i/o. ? bus interface characteristics ? 24-bit (16 mb) address output ? 6 individual banks using chip selection function random positional setting is possible on the logical address space at minimum 64-kb units. total 16 mb 6 areas can be set using the address pin and chip selection pin. ? 16/8-bit bus width can be set per chip selection area. ? insertion of programmable automatic memory wait (maximum of 7 cycles) ? supports dram interface 3 types of dram interface double cas dram (normal dram i/f) single cas dram hyper dram 2-bank individual control (control signal i.e. ras and cas) dram can be selected from 2cas/1we or 1cas/2we. supports high-speed page mode supports cbr / self refresh programmable corrugation ? unused addresses / data pins can be used as i/o ports. ? supports little endian mode ? using clock doubler : internal 50 mhz, external bus 25 mhz operation ? chip selection area a total of six types of chip selection areas are prepared for the bus interface. the position of each area can be randomly arranged per 64 kb at least using area selection registers (asr1 to 5) and area mask registers (amr1 to 5) in an area of 4 gb. in the event that access to an external bus is attempted in areas that are specified by those registers, the supported chip selection signals (cs0 to cs5 ) become activated to l. such pins other than cs0 are deactivated to h when reset. note : the area 0 is allocated to space outside the area specified by asr1 to asr5. external areas other than 0001 0000 h to 0005 ffff h are deemed area 0 on resetting.
MB91110 series 41 ? interface the bus interface has the following interface types. ? normal bus interface ?dram interface these interfaces can only be used in predetermined areas. the following table shows each chip selection area and the usable interface functions.which interface is to be used is selected in the area mode register (amd) . if no selection is made, it defaults to the normal bus interface. chip selection area and selectable bus interfaces ? block diagram areas selectable bus interface remarks normal bus time division dram 0 ?? on resetting 1 ?? 2 ?? 3 ?? 4 ? 5 ? a-out mux inpage cs0 ~ cs5 ras0, ras1 cs0l, cs1l cs0h, cs1h dw0, dw1 rd wr0, wr1 brq bgrnt clk rdy 32 32 address bus data bus write buffer read buffer switch switch external data bus + 1or + 2 address buffer asr amr shifter comparator data block address block external address bus dram control underflow dmcr from tbt refresh counter external pin control area controls all blocks registers & control
MB91110 series 42 ? register list *1 : amd (area mode register) *2 : dscr (dram signal control register) *3 : ler (little endian register) *4 : modr (mode register) address initial value access 00060c h 00060e h 00000000 00000001 b 00000000 00000000 b w w 000610 h 000612 h 00000000 00000010 b 00000000 00000000 b w w 000614 h 000616 h 00000000 00000011 b 00000000 00000000 b w w 000618 h 00061a h 00000000 00000100 b 00000000 00000000 b w w 00061c h 00061e h 00000000 00000101 b 00000000 00000000 b w w 000620 h 000622 h - - - 00111 0- - 00000 b 00000000 0- - 00000 b r/w r/w 000624 h 000626 h 0- - 00000 00000000 b - -xxxxxx 0- - - 0000 b r/w r/w 000628 h 00062a h - - - - 1100 - 0000000 b - - - - - - - - 11111111 b w w 00062c h 00062e h 00000000 0000000- b 00000000 0000000- b r/w r/w 0007fc h - - - - - - 00 xxxxxxxx b w amr1 (area mode reg. 1) amr2 (area mode reg. 2) asr1 (area select reg. 1) asr2 (area select reg. 2) amr3 (area mode reg. 3) asr3 (area select reg. 3) amr4 (area mode reg. 4) amr5 (area mode reg. 5) asr4 (area select reg. 4) asr5 (area select reg. 5) rfcr (refresh control register) epcr1 (external pin control 1) epcr0 (external pin control 0) dmcr5 (dram control reg. 5) dmcr4 (dram control reg. 4) ler * 3 modr * 4 amd32 * 1 amd4 * 1 amd0 * 1 amd1 * 1 amd5 * 1 dscr * 2 15 8 7 0 31 24 23 16
MB91110 series 43 8. 16-bit reload timer the 16-bit timer is composed of a 16-bit down counter, 16-bit reload register, a pre-scalar for internal count clock preparation and a control register. selection of the input clock can be made from three types of internal clock (machine clocks with 2, 8 and 32 cycles) and an external clock are selectable for input clock. ? characteristics of the 16-bit reload timer the pin output (to) outputs a toggle waveform whenever underflow is generated in reload mode, and outputs rectangular waves indicating that it is counting in the case of one shot mode. pin input (ti) can be used for event input in the case of external event count mode, trigger input or gate input for internal clock mode. if the external event count function is used as the reload mode, it can be used as the cycle device for the external clock. in this type, a 2-channel timer is built-in. channel 0 of the reload timer can start up dma transfer using the interruption request signal. the dma controller clears the interruption flag of the reload timer at the same time as receiving the transfer request. the to output from channel 0 for the reload timer is connected to the a/d converter inside the lsi. thus, a/d conversion can be started on a cycle set at the reload register.
MB91110 series 44 ? block diagram ? register list reld oute outl inte uf cnte trg out ctl. csl1 csl0 mod2 mod1 mod0 16 8 16 2 3 2 in ctl. f 2 f 2 f 2 1 35 3 exck gate uf 2 irq r | b u s 16-bit reload register reload 16-bit down counter clock selector re- trigger port (ti) port (to) pre-scalar clear internal clock ? control status register (tmcsr) ? 16-bit timer register (tmr) ? 16-bit reload register (tmrlr) address initial value access 000036 h - - - - 0000 b r/w 000037 h 00000000 b r/w address initial value access 00002a h 000032 h xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b w address initial value access 000028 h 000030 h xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b w 15 14 13 12 11 10 9 8 ? ??? csl1 csl0 mod2 mod1 7654 321 0 oute mod0 outl reld inte uf cnte trg 15 0 15 0
MB91110 series 45 9. ppg timer the ppg timer can output pulses that are synchronized with soft triggers or externally. also, the cycle and duty of the output pulses can be changed randomly by replacing the two 16-bit register values. in this type, there are 6 built-in channels with this function. ? ppg timer function the ppg timer has two functions as follows. ? pwm function this can be synchronized to the trigger and is programmable to output pulses while rewriting the above register values. it can also be used as a d/a converter by using an additional circuit. ? one-shot function this detects the edge of the trigger input and outputs a single pulse. ? block diagram f / 2 f / 8 f / 32 f / 128 ck pcsr pdut cmp s r q irq pre-scalar load 16-bit down counter start borrow ppg mask ppg output reverse bit enable trg input (only channels 0 to 2) edge detection soft trigger interrup- tion selection
MB91110 series 46 ?register list ? cycle setting register (pcsr) ? duty setting register (pdut) ? control/status register (pcnh/pcnl) address initial value access 000046 h 00004e h 000056 h 00005e h 000066 h 00006e h xxxxxxxx xxxxxxxx b w address initial value access 000048 h 000050 h 000058 h 000060 h 000068 h 000070 h xxxxxxxx xxxxxxxx b w address initial value access 00004a h 000052 h 00005a h 000062 h 00006a h 000072 h 0000000 - 00000000 b r/w 15 8 7 0 bit 15 8 7 0 bit 15 8 7 0 bit
MB91110 series 47 10. external interruption/nmi control area the external interruption / nmi control area controls the external interruption requests to be input to the nmi and int0 to int7. h or l and rising edge or falling edge can be selected as the requested detection level (except for nmi) . also, four requests from int0 to int3 can be used as the dma request. ? block diagram ? register list 9 9 int0 ~ int7 nmi 8 8 8 r bus interruption requests interruption permission register gate factor f/f edge detection circuit interruption factor register request level setting register ? external interruption permission register (enir) ? external interruption factors register (eirr) ? request level setting register (elvr) address bit initial value access 000095 h 00000000 b r/w address bit 000094 h 00000000 b r/w address bit 000098 h 00000000 b r/w bit 000099 h 00000000 b r/w 7654 321 0 en6 en7 en5 en4 en3 en2 en1 en0 15 14 13 12 11 10 9 8 er6 er7 er5 er4 er3 er2 er1 er0 15 14 13 12 11 10 9 8 la7 lb7 lb6 la6 lb5 la5 lb4 la4 7654 321 0 la3 lb3 lb2 la2 lb1 la1 lb0 la0
MB91110 series 48 11. delay interruption modules this is a module to generate interruptions to switch tasks. this module can be used with software to generate / cancel interruption requests to the cpu. ? block diagram ? register list write icr icr il ilm cpu cmp cmp dicr resource request delay interruption interruption controller address initial value access 000430 h - - - - - - - 0 b r/w bit 654 3 21 0 ? ?????? dlyi 7
MB91110 series 49 12. interruption controller the interruption controller carries out interruption reception and arbitration. ? hardware configuration of the interruption controller this module is configured for the following items. ? icr register ? interruption priority judgement circuit ? interruption level, interruption number (vector) generation area ? cancellation request generation area for hold request ? major interruption controller functions this module has the following functions. ? detection of nmi request / interruption request ? priority grade judgement (depending on the level and number) ? transferring interruption level of factors for the judgement results (to cpu) ? transferring interruption number of factors for the judgement results (to cpu) ? recovery instruction from stop mode by generating nmi / interruption ? cancellation of hold request to the bus master
MB91110 series 50 ? block diagram int0* 2 or nmi ri00 ri47 (dlyirq) dlyi* 1 4 5 6 level 4 ~ 0 hldcan* 3 vct5 ~ 0 r-bus im icr00 icr47 *1 : dlyi indicates delay interruption. (refer to the chapter on delay interruption module for details.) *2 : into is the wake-up signal to the clock control area in case of sleep or stop. *3 : hldcan is the bus vacation request signal to bus masters other than the cpu. priority grade judgement nmi processing level judgement vector judgement genera- tion of level vector cancella- tion re- quest for holding
MB91110 series 51 ? register list address bit 7 6 5 4 3 2 1 0 initial value acces 000400 h ??? icr4 icr3 icr2 icr1 icr0 icr00 - - - 11111 r/w 000401 h ??? icr4 icr3 icr2 icr1 icr0 icr01 - - - 11111 r/w 000402 h ??? icr4 icr3 icr2 icr1 icr0 icr02 - - - 11111 r/w 000403 h ??? icr4 icr3 icr2 icr1 icr0 icr03 - - - 11111 r/w 000404 h ??? icr4 icr3 icr2 icr1 icr0 icr04 - - - 11111 r/w 000405 h ??? icr4 icr3 icr2 icr1 icr0 icr05 - - - 11111 r/w 000406 h ??? icr4 icr3 icr2 icr1 icr0 icr06 - - - 11111 r/w 000407 h ??? icr4 icr3 icr2 icr1 icr0 icr07 - - - 11111 r/w 000408 h ??? icr4 icr3 icr2 icr1 icr0 icr08 - - - 11111 r/w 000409 h ??? icr4 icr3 icr2 icr1 icr0 icr09 - - - 11111 r/w 00040a h ??? icr4 icr3 icr2 icr1 icr0 icr10 - - - 11111 r/w 00040b h ??? icr4 icr3 icr2 icr1 icr0 icr11 - - - 11111 r/w 00040c h ??? icr4 icr3 icr2 icr1 icr0 icr12 - - - 11111 r/w 00040d h ??? icr4 icr3 icr2 icr1 icr0 icr13 - - - 11111 r/w 00040e h ??? icr4 icr3 icr2 icr1 icr0 icr14 - - - 11111 r/w 00040f h ??? icr4 icr3 icr2 icr1 icr0 icr15 - - - 11111 r/w 000410 h ??? icr4 icr3 icr2 icr1 icr0 icr16 - - - 11111 r/w 000411 h ??? icr4 icr3 icr2 icr1 icr0 icr17 - - - 11111 r/w 000412 h ??? icr4 icr3 icr2 icr1 icr0 icr18 - - - 11111 r/w 000413 h ??? icr4 icr3 icr2 icr1 icr0 icr19 - - - 11111 r/w 000414 h ??? icr4 icr3 icr2 icr1 icr0 icr20 - - - 11111 r/w 000415 h ??? icr4 icr3 icr2 icr1 icr0 icr21 - - - 11111 r/w 000416 h ??? icr4 icr3 icr2 icr1 icr0 icr22 - - - 11111 r/w 000417 h ??? icr4 icr3 icr2 icr1 icr0 icr23 - - - 11111 r/w 000418 h ??? icr4 icr3 icr2 icr1 icr0 icr24 - - - 11111 r/w 000419 h ??? icr4 icr3 icr2 icr1 icr0 icr25 - - - 11111 r/w 00041a h ??? icr4 icr3 icr2 icr1 icr0 icr26 - - - 11111 r/w 00041b h ??? icr4 icr3 icr2 icr1 icr0 icr27 - - - 11111 r/w 00041c h ??? icr4 icr3 icr2 icr1 icr0 icr28 - - - 11111 r/w 00041d h ??? icr4 icr3 icr2 icr1 icr0 icr29 - - - 11111 r/w 00041e h ??? icr4 icr3 icr2 icr1 icr0 icr30 - - - 11111 r/w 00041f h ??? icr4 icr3 icr2 icr1 icr0 icr31 - - - 11111 r/w 000420 h ??? icr4 icr3 icr2 icr1 icr0 icr32 - - - 11111 r/w 000421 h ??? icr4 icr3 icr2 icr1 icr0 icr33 - - - 11111 r/w 000422 h ??? icr4 icr3 icr2 icr1 icr0 icr34 - - - 11111 r/w 000423 h ??? icr4 icr3 icr2 icr1 icr0 icr35 - - - 11111 r/w 000424 h ??? icr4 icr3 icr2 icr1 icr0 icr36 - - - 11111 r/w 000425 h ??? icr4 icr3 icr2 icr1 icr0 icr37 - - - 11111 r/w 000426 h ??? icr4 icr3 icr2 icr1 icr0 icr38 - - - 11111 r/w 000427 h ??? icr4 icr3 icr2 icr1 icr0 icr39 - - - 11111 r/w 000428 h ??? icr4 icr3 icr2 icr1 icr0 icr40 - - - 11111 r/w 000429 h ??? icr4 icr3 icr2 icr1 icr0 icr41 - - - 11111 r/w 00042a h ??? icr4 icr3 icr2 icr1 icr0 icr42 - - - 11111 r/w 00042b h ??? icr4 icr3 icr2 icr1 icr0 icr43 - - - 11111 r/w 00042c h ??? icr4 icr3 icr2 icr1 icr0 icr44 - - - 11111 r/w 00042d h ??? icr4 icr3 icr2 icr1 icr0 icr45 - - - 11111 r/w 00042e h ??? icr4 icr3 icr2 icr1 icr0 icr46 - - - 11111 r/w 00042f h ??? icr4 icr3 icr2 icr1 icr0 icr47 - - - 11111 r/w r r/w r/w r/w r/w 000431 h ??? lvl4 lvl3 lvl2 lvl1 lvl0 hrcl - - - 11111 r/w r r/w r/w r/w r/w
MB91110 series 52 13. interruption control register (icr) this function is set up per interruption input and sets the interruption level of interruption requests to be handled. ? register list [bit 4 to 0] icr4 to 0 the interruption level of the interruption requests that are handled is specified by the interruption level setting bit. in cases where the interruption level that is set in this register is the same as or more than the level mask value that is set (has been set) in the ilm register of the cpu, the interruption request is masked at the cpu side. it is initialized to 11111 b on resetting. the settable interruption level setting bit and interruption level are shown in following table. interruption level setting bit and interruption level note: icr 4 is fixed as 1 and can not be written as 0. icr4 icr3 icr2 icr1 icr0 interruption level 000000 system reservation 0111014 0111115nmi 1 0 0 0 0 16 maximum settable level 1000117 (high) 1001018 1001119 1010020 1010121 1011022 1011123 1100024 1100125 1101026 1101127 1110028 1110129 1111030 (low) 1 1 1 1 1 31 interruption is prohibited bit 7 6 5 4 3 2 1 0 r/w ? ?? icr4 icr3 icr2 icr1 r r/w r/w r/w icr0
MB91110 series 53 14. 10-bit a/d converter the a/d converter is the module that converts analog input voltages to a digital value. ? characteristics of a/d converter ? minimum converting time : 5.6 m s/channel ? sample & hold circuit is built-in. ? resolution : 10 bits ? selection can be made for analog input from 8 channels. ? initiation of dma transfer by interruption is possible. ? initiation factor can be selected from software, external trigger (falling edge) or reload timer (rising edge) . ? block diagram single conversion mode : 1 channel is selected for conversion scan conversion mode : converts multiple number of consecutive channels. maximum 8 channels are programmable. consecutive conversion mode : repeatedly converts the specified channel. suspension / conversion mode : suspends after converting 1 channel and waits until the next one is started up (synchronization for starting conversion is possible) av cc avr av ss mpx an0 an1 an2 an3 atg f an4 an5 an6 an7 adcr adcs r | b u s input circuit internal voltage generator data register a/d control register 1 starting up external trigger sequential comparison register sample & hold circuit comparator decoder tim0 (internal connection) (reload timer channel 0) starting up timer (peripheral system clock) operation clock pre-scalar
MB91110 series 54 ? register list ? control status register (adcs) ? data register (adcr) address bit initial value access 00003a h 00000000 b r/w bit 00003b h 00000000 b r/w address bit initial value access 000038 h - - - - - - xx b r bit 000039 h xxxxxxxx b r 15 14 13 12 11 10 9 8 int busy inte paus sts1 sts0 strt ? 7654 321 0 md0 md1 ans2 ans1 ans0 ane2 ane1 ane0 15 14 13 12 11 10 9 8 ? ????? 98 7654 321 0 6 7 5 43210
MB91110 series 55 15. uart uart is the serial i/o port for carrying out asynchronous (start-stop synchronization) or clk synchronous communication. ? characteristics of uart ? fdx double buffer ? asynchronous (start-stop synchronization) and clk synchronous communication are possible. ? supports multi processor mode ? dedicated baud rate generator is built-in. ? free baud rate can be set using an external clock. ? error detection function (parity, framing, overrun) ? transfer signal is nrz code ? initiation of dma transfer is possible by interruption.
MB91110 series 56 ? block diagram si md1 md0 cs2 cs1 cs0 scke soe pen p sbl cl a / d rec rxe txe pe ore fre rdrf tdre rie tie r - bus sidr sodr so sck control signal control signal dedicated baud rate generator 16-bit reload timer (internal connection) external clock start bit detection circuit reception bit counter reception parity counter clock selection circuit reception status judgement circuit reception error generation signal for dma (to dmac) smr register scr register ssr register reception clock reception control circuit shifter for reception shifter for transmission end of reception start transmission reception interruption (to cpu) transmission interruption (to cpu) transmission clock transmission control circuit transmission starting circuit transmission bit counter transmission parity counter
MB91110 series 57 ? register list ? serial mode register (smr) ? serial control register (scr) ? serial input data register/serial output data register (sidr/sodr) ? serial status register (ssr) ? communication pre-scalar control register (cdcr) address bit initial value access 000023 h 00000 - 00 b r/w bit initial value access 000022 h 00000100 b r/w bit initial value access 000021 h xxxxxxxx b r/w bit initial value access 000020 h 00001 - 00 b r/w bit initial value access 000025 h 0 - - 11111 b r/w 7654 321 0 md0 md1 cs2 cs1 cs0 ? scke soe 15 14 13 12 11 10 9 8 p pen sbl cl a/d rec rxe txe 7654 321 0 d6 d7 d5 d4 d3 d2 d1 d0 15 14 13 12 11 10 9 8 ore pe fre rdrf tdre ? rie tie 7654 321 0 ? md ? div4 div3 div2 div1 div0
MB91110 series 58 16. dma controller (dmac) the dma controller is the module to realize direct memory access (dma) transfers with fr 30 series devices. dma transfers controlled by this module enable quick and direct transfer of all data without using the cpu and thus system performance is increased. ? hardware configuration of dma controller this module is mainly configured of the following items. ? internal i/o access control circuit ? 32-bit address counters (possible reload specification : 10) ? 16-bit transfer number counters (possible reload specification : 5) ? external transfer request input pin : dreq0, dreq1, dreq2 ? external transfer request reception output pin : dack0, dack1, dack2 (external bus synchronization) ? external transfer termination output pin : deop0, deop1, deop2 (external bus synchronization) ? major function of dma controller there are the following functions for data transfer using this module. ? independent data transfer of a number of channels is possible (5 ch) ? priority ranking amongst channels fixed ranking (ch.0 > ch.1 > ch.2 > ch.3 > ch.4) ranking between channel 0 and 1 can be reversed. ? transfer request dedicated external pin input (edge detection / level detection selection are possible for channels 0 to 2 only.) built-in peripheral request (interruption requests are shared. external interruption is included.) software request (register writing) ? transfer sequence consecutive / burst transfer step transfer / block transfer (maximum 16 words are settable.) ? addressing mode : 32-bit full address specification (increase / decrease / fix) ? data types : byte, half word, word length ? single shot or reload can be selected.
MB91110 series 59 ? block diagram dreq0 dreq1 dreq2 dack0 dack1 dack2 deop0 deop1 deop2 ack. fr30 cpu d - bus external transfer request input detection / processing external transfer request transfer request processing each channel request peripheral interruption request peripheral interruption request controls arbitration of requests, priority judgement and decision on transferring channels transfer start request channel instruction hold control hold request transfer state machine (bus control) end data control external input setting each channel request setting each channel transfer mode setting each channel address generation control address counter control counting address / the number of times counter of the number of transfer times interruption control address no. of times input setting register request setting register mode setting register address control register address registers no. of times registers data buffer
MB91110 series 60 ?register list *: shaded areas indicate where nothing exists. address bit 31 0 initial value access 000200 h ch.0 control / status register dmacs0 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0 b xx - 0 0 0 0 0 - - - - xx - x b r/w 000204 h ch.0 addressing/transfer counting register dmacc0 - - - - xxxx xxxx - xxx b xxxxxxxx xxxxxxxx b r/w 000208 h ch.0 transfer originator address register dmasa0 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 00020c h ch.0 destination address register dmada0 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 000210 h ch.1 control / status register dmacs1 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0 b xx - 0 0 0 0 0 - - - - xx - x b r/w 000214 h ch.1 addressing/transfer counting register dmacc1 - - - - xxxx xxxx - xxx b xxxxxxxx xxxxxxxx b r/w 000218 h ch.1 transfer originator address register dmasa1 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 00021c h ch.1 destination address register dmada1 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 000220 h ch.2 control / status register dmacs2 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0 b xx - 0 0 0 0 0 - - - - xx - x b r/w 000224 h ch.2 addressing/transfer counting register dmacc2 - - - - xxxx xxxx - xxx b xxxxxxxx xxxxxxxx b r/w 000228 h ch.2 transfer originator address register dmasa2 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 00022c h ch.2 destination address register dmada2 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 000230 h ch.3 control / status register dmacs3 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0 b xx - 0 0 0 0 0 - - - - xx - x b r/w 000234 h ch.3 addressing/transfer counting register dmacc3 - - - - xxxx xxxx - xxx b xxxxxxxx xxxxxxxx b r/w 000238 h ch.3 transfer originator address register dmasa3 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 00023c h ch.3 destination address register dmada3 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 000240 h ch.4 control / status register dmacs4 0 - 0 0 - 0 0 0 0 0 - - 0 0 0 0 b xx - 0 0 0 0 0 - - - - xx - x b r/w 000244 h ch.4 addressing/transfer counting register dmacc4 - - - - xxxx xxxx - xxx b xxxxxxxx xxxxxxxx b r/w 000248 h ch.4 transfer originator address register dmasa4 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 00024c h ch.4 destination address register dmada4 xxxxxxxx xxxxxxxx b xxxxxxxx xxxxxxxx b r/w 000250 h overall control register dmacr - - - - - - - - - - - - - - - - b 0 0 - - - - - - - - - - - - - 0 b r/w
MB91110 series 61 17. bit search module bit search module searches for 0, 1 or change points on data that has been written in the input register, and returns the detected bit position. ? block diagram ? registers list 18. i-ram this type has 16 kb of built-in i-ram (ram dedicated for instructions) . efficient processing becomes possible by pre-arranging interruption processing programs and such like in this area. writing on i-ram is possible via the data bus and is used in case of debugging. ? register list d-bus input latch address decoder detection mode changing to 1 detection data bit search circuit detection results address 31 0 initial value access 0003f0 h data register for 0 detection (bsd0) xxxxxxxx xxxxxxx b xxxxxxxx xxxxxxx b w 0003f4 h data register for 1 detection (bsd1) xxxxxxxx xxxxxxx b xxxxxxxx xxxxxxx b r/w 0003f8 h data register for change point detection (bsdc) xxxxxxxx xxxxxxx b xxxxxxxx xxxxxxx b w 0003fc h detection results register (bsrr) xxxxxxxx xxxxxxx b xxxxxxxx xxxxxxx b r irmc initial value access address : 0003ef h - - - - - - - 0 r/w 7654 321 0 ? ? ? ???? irmd
MB91110 series 62 n n n n electrical characteristics 1. absolute maximum ratings (v ss = av ss = avrl = 0 v) *1 : v cc 3/v cc 5 must not be lower than v ss - 0.3 v. *2 : care must be taken that this does not exceed v cc + 0.3 v when the power is turned on. *3 : peak value of the pin concerned is regulated as the maximum output current. *4 : average current within 100 ms flowing in the pin concerned is regulated as the average output current. *5 : average current within 100 ms flowing in all pins concerned is regulated as the average total output current. warning: semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. do not exceed these ratings. parameter symbol rating unit remarks min. max. power voltage v cc 5v cc 3 - 0.3 v ss + 6.0 v *1 v cc 3v ss - 0.3 v ss + 3.6 v *1 analog power voltage av cc v ss - 0.3 v ss + 3.6 v *2 standard analog voltage avrh v ss - 0.3 v ss + 3.6 v *2 input voltage v i v ss - 0.3 v cc 5 + 0.3 v analog pin input voltage v ia v ss - 0.3 av cc + 0.3 v output voltage v o v ss - 0.3 v cc 5 + 0.3 v maximum l level output current i ol ? 10 ma *3 average l level output current i olav ? 4ma*4 maximum total l level output current s i ol ? 100 ma average l level total output current s i olav ? 50 ma *5 maximum h level output current i oh ?- 10 ma *3 average h level output current i ohav ?- 4ma*4 maximum total h level output current s i oh ?- 50 ma average h level total output current s i ohav ?- 20 ma *5 electricity consumption p d ? 650 mw operating temperature t a 0 + 70 c storage temperature tstg - 55 + 150 c
MB91110 series 63 2. recommended operating conditions (v ss = av ss = avrl = 0 v) warning: the recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. all of the devices electrical characteristics are warranted when the device is operated within these ranges. always use semiconductor devices within their recommended operating condition ranges. operation outside these ranges may adversely affect reliability and could result in device failure. no warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. users considering application outside the listed conditions are advised to contact their fujitsu representatives beforehand. parameter symbol value unit remarks min. max. power voltage v cc 54.5 5.5 v keeping ram status in the case of normal operations / stopping v cc 3 3.135 3.465 analog power voltage av cc v ss - 3.0 v ss + 3.465 v standard analog voltage avrh av ss av cc v operating temperature t a 0 + 70 c
MB91110 series 64 3. dc characteristics (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) * : hysteresis input pins : rst , hst , nmi , pe0/atg , pe1/trg0, 3, pe2/trg1, 4, pe3/trg2, 5, pf0/int0 to pf7/int7, pg0/dreq0, pg3/dreq1, ph0/dreq2, ph3/si, ph5/sck, ph6/ti0, pi0/ti1, bgrnt /p81, wr1 /p85, cs1 /pa0 to clk/pa6, ras0/pb0 to dw1 /pb7 parameter sym bol pin name conditions value unit remarks min. typ. max. h level input voltage v ih input excluding following ? 0.65 v cc 3 ? v cc 5 + 0.3 v v ihs refer to * ? 0.8 v cc 3 ? v cc 5 + 0.3 v hysteresis input l level input voltage v il input excluding following ? v ss - 0.3 ? 0.25 v cc 3 v v ils refer to * ? v ss - 0.3 ? 0.2 v cc 3 v hysteresis input h level output voltage v oh ? v cc 5 = 4.5 v i oh = - 4.0 ma v cc 5 - 0.5 ?? v l level output voltage v ol ? v cc 5 = 4.5 v i ol = 4.0 ma ?? 0.4 v input leak current (hi-z output leak current) i li ? v cc 5 = 5.5 v 0.45 v < v i < v cc 5 - 5 ?+ 5 m a pull-up resistance value r pull rst v cc 5 = 5.5 v v i = 0.45 v 25 50 200 k w power current i cc v cc 5f c = 12.5 mhz v cc 5 = 5.5 v v cc 3 = 3.465 v ? 50 70 ma (4 times) in case of 50 mhz operation v cc 3 ? 100 150 ma i ccs v cc 5f c = 12.5 mhz v cc 5 = 5.5 v v cc 3 = 3.465 v ? 20 30 ma in case of sleeping v cc 3 ? 50 70 ma i cch v cc 5t a = 25 c v cc 5 = 5.5 v v cc 3 = 3.465 v ? 10 20 m a in case of stopping v cc 3 ? 200 900 m a input capacity c in other than v cc , a vcc , a vss and v ss ?? 10 ? pf
MB91110 series 65 4. ac characteristics measurement conditions the following conditions are applied to items without particular specifications. v oh v ol v ih v il v cc 5 0 v input output v ih 2.4 v v oh 2.4 v v il 0.8 v v ol 0.8 v c = 50 pf output pin ? alternating current standard measurement condition v cc 5 : 5.0 v 10 % ? load condition
MB91110 series 66 (1) clock timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) *1 : frequency fluctuation rate indicates the maximum fluctuation ratio from the setting central frequency during locking in case of doubling. *2 : this is the value when 10 mhz, which is the minimum value of the clock frequency, is input to x0 and 1/2 cycle of the oscillation circuit and gearing of 1/8 are used. *3 : this is the value when doubler is used with a 50 mhz cpu. parameter sym- bol pin name conditions value unit remarks min. max. clock frequency (1) f c x0 x1 ? 10.0 12.5 mhz self oscillation 12.5 mhz internal 50 mhz operation (via pll, 4 times) clock cycle time t c x0 x1 80 100 ns frequency fluctuation rate* 1 (when locked) d f ?? 5 % clock frequency (2) f c x0 x1 ? 10 25 mhz self oscillation (1/2 cycle input) clock frequency (3) f c x0 x1 10 25 mhz external clock (1/2 cycle input) clock cycle time t c x0 x1 40 100 ns input clock pulse width p wh p wl x0 x1 10 ? ns clock is input to x0/x1 p wh x0 25 ? ns clock is input to x0 only input clock rising/falling time t cr t cf x0 x1 ?? 8ns (t cr + t cf ) internal operation clock frequency f cp ? 0.625* 2 50 mhz cpu system f cpb 0.625* 2 25* 3 bus system f cpp 0.625* 2 25 peripheral system internal operation clock cycle time t cp 20 1600* 2 ns cpu system t cpb 40* 3 1600* 2 bus system t cpp 40 1600* 2 peripheral system +a -a central frequency f o d f = 100 ( % ) a f o
MB91110 series 67 ? clock timing standard measurement conditions ? guaranteed operating area 0.8 v cc 5 0.2 v cc 5 t cf t cr t c p wh p wl 050 25 (mhz) 0.625 3.465 3.135 5.5 4.5 f cp / f cpp v cc 3 v cc 5 power voltage internal clock guaranteed operating area (t a = 0 ~ + 70 c) f cpp is the shaded area.
MB91110 series 68 ? external/internal clock settable area notes: 10.0 mhz to 12.5 mhz must be input for external clock input when pll is used. pll oscillation stabilization time should be larger than 100 m s. internal clock gear should be set within the above range. 50 40 20 12.5 0 0 25 f c (mhz) f cp / f cpp (mhz) 5 f cp 12.5 f cpp 25 10 cpu pll system (12.5 mhz / 4 times) 1/2 cycle system external clock self oscillation original oscillation input clock peripheral internal clock settable limit
MB91110 series 69 (2) clock output timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) *1 : t cyc is frequency of 1 clock cycle including the gear cycle. *2 : this standard value is in the case where the gear cycle is 1. if the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. minimum : (1 - n / 2) t cyc - 10 maximum : (1 - n / 2) t cyc + 10 gear cycle of 1 should be taken when using a doubler. *3 : this standard value is in the case where the gear cycle is 1. if the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. minimum : n / 2 t cyc - 10 maximum : n / 2 t cyc + 10 gear cycle of 1 should be taken when using a doubler. parameter sym- bol pin name condi- tions value unit remarks min. max. cycle time t cyc clk ? t cp ? ns *1 2 t cp ? in case of using doubler clk - ? clk t chcl clk 1 / 2 t cyc - 10 1 / 2 t cyc + 10 ns *2 clk ? clk - t clch clk 1 / 2 t cyc - 10 1 / 2 t cyc + 10 ns *3 clk v oh v ol v oh t cyc t clch t chcl
MB91110 series 70 the relationship between the clk pin set using chc/cck1/cck0 bit of the gear control register (gcr) and original oscillation input is as follows. however, original oscillation input indicates x0 input clock in this figure. t cyc cck1/0 : "00" slct1, 0 : 01 cck1, 0 : 01 slct1, 0 : 1x t cyc t cyc t cyc t cyc ? pll system (chc bit of gcr : 0setting) ? 2 cycles system (chc bit of gcr : 1setting) (when using doubler) or original oscillation input (a) gear 1 clk pin original oscillation input (a) gear 1 clk pin cck1/0: 00 (b) gear 1/2 clk pins cck1/0: 01 (c) gear 1/4 clk pins cck1/0: 10 (d) gear 1/8 clk pins cck1/0: 11
MB91110 series 71 (3) reset / hardware standby input (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) parameter sym- bol pin name conditions value unit remarks min. max. reset input time t rstl rst ? t cp 5 ? ns hardware standby input time t hstl hst ? t cp 5 ? ns rst 0.2 v cc 5 t rstl , t hstl hst
MB91110 series 72 (4) power on reset (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) parameter sym- bol pin name conditions value unit remarks min. max. power startup time t r v cc 5 v cc 5 = 5 v ? 30 ms v cc is less than 0.2 v before power is turned on. v cc 3 = 3.3 v 18 power cut time t off v cc 3 ? 1 ? ms repeated operation waiting time for oscillation stabilization t osc ?? 2 t c 2 21 + 100 m s ? ns v cc 3 v ss v cc 3 rst t rstl v cc 5 0.2 v cc 3 t r 0.9 v cc 3 v cc 3 t off t osc (waiting time for oscillation stabilization) other points to note (1) sudden changes in the power supply voltage may cause a power-on reset .to change the power supply voltage while the device is in operation, it is recommended to rise the voltage smoothly to suppress fluctuations as shown below. (2) when power is turned on, it must be started while the rst pin is set to l level, after which wait for t rstl and change the level to h once the vcc power level is reached. it is recommended to keep the rising speed of the supply voltage at 50 mv/ms or slower. v cc 3 / av cc / avrh should be supplied after supplying v cc 5. av cc / avrh should be supplied at the same time after supplying v cc 3.
MB91110 series 73 (5) normal bus access read/write operation (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) *1 : time (t cyc number of cycles extended) needs to be added to this standard if the bus is extended by automatic waiting insertion and rdy input. *2 : values of this standard are in case of gear cycle 1. if the gear cycle is set to 1/2, 1/4 or 1/8, calculations should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. calculation formula : (2 - n / 2) t cyc - 40 parameter sym- bol pin name condi- tions value unit remarks min. max. cs0 to cs5 delay time t chcsl clk cs0 to cs5 ? ? 15 ns cs0 to cs5 delay time t chcsh ? 15 ns address delay time t chav clk a23 to a00 ? 15 ns data delay time (write) t chdv clk d31 to d16 ? 15 ns rd delay time t clrl clk rd ? 10 ns rd delay time t clrh ? 10 ns wr0 to wr1 delay time t clwl clk wr0 to wr 1 ? 10 ns wr0 to wr1 delay time t clwh ? 10 ns valid address ? valid data input time read t avdv a23 to a00 d31 to d16 ? 3 / 2 t cyc - 40 ns *1 *2 rd ? valid data input time t rldv rd d31 to d16 ? t cyc - 25 ns *1 data setup ? rd - time t dsrh 25 ? ns rd - ? data holding time t rhdx 0 ? ns
MB91110 series 74 2.4 v clk 0.8 v 2.4 v 0.8 v 0.8 v ba2 2.4 v 0.8 v 2.4 v 0.8 v t clrl 0.8 v t clwl 0.8 v t chdv 0.8 v 2.4 v 0.8 v 2.4 v t clrh 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v t dsrh t rhdx t clwh 2.4 v 2.4 v 0.8 v t chcsh 2.4 v cs0 ~ cs5 a23 ~ a00 rd d31 ~ d16 wr0 ~ wr1 d31 ~ d16 ba1 t cyc t chcsl t rldv t avdv t chav read write
MB91110 series 75 (6) ready input timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) parameter sym- bol pin name conditions value unit remarks min. max. rdy setup time ? clk t rdys rdy clk ? 20 ? ns clk ? rdy holding time t rdyh rdy clk 0 ? ns clk 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v t rdyh t rdyh rdy rdy t cyc t rdys t rdys (if " wait " is executed) (if " wait " is not executed)
MB91110 series 76 (7) holding timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) note : it takes at least one cycle from loading the brq to when bgrnt is changed. parameter sym- bol pin name condi- tions value unit remarks min. max. bgrnt delay time t chbgl clk bgrnt ? ? 10 ns bgrnt delay time t chbgh ? 10 ns pin floating ? bgrnt time t xhal bgrnt t cyc - 10 t cyc + 10 ns bgrnt - ? pin valid time t hahv t cyc - 10 t cyc + 10 ns clk 2.4 v t chbgl 0.8 v 2.4 v 2.4 v 2.4 v 2.4 v t chbgh brq bgrnt each pin t cyc t hahv t xhal high impedance
MB91110 series 77 (8) read/write cycle of the normal dram mode (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) *1 : if either the q1 or a4 cycle is extended for one cycle, the t cyc time needs to be added to this standard. *2 : values of this standard are in case of gear cycle 1. if the gear cycle is set to 1/2, 1/4 or 1/8, calculation should be made using the following formula and replacing n with 1/2, 1/4 or 1/8. calculation formula : (3 - n / 2) t cyc - 20 parameter sym- bol pin name condi- tions value unit remarks min. max. ras delay time t clrah clk ras ? ? 10 ns ras delay time t chral ? 10 ns cas delay time t clcasl clk cas ? 10 ns cas delay time t clcash ? 10 ns row address delay time t chrav clk a23 to a00 ? 15 ns column address delay time t chcav ? 15 ns dw delay time t chdwl clk dw ? 15 ns dw delay time t chdwh ? 15 ns output data delay time t chdv1 clk d31 to d16 ? 15 ns ras ? valid data input time t rldv ras d31 to d16 ? 5 / 2 t cyc - 20 ns *1 *2 cas ? valid data input time t cldv cas d31 to d16 ? t cyc - 17 ns *1 cas - ? data holding time t cadh 0 ? ns
MB91110 series 78 0.8 v 2.4 v 0.8 v 2.4 v d31 ~ d16 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 2.4 v clk 0.8 v q2 q1 q3 q4 q5 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v t chral 0.8 v t clcasl 2.4 v t chrav 0.8 v 2.4 v 0.8 v 2.4 v t cadh 0.8 v 2.4 v t chdwl t chdwh t chdv1 d31 ~ d16 ras cas a23 ~ a00 dw t cyc t clrah t chcav t clcash t rldv t cldv 0.8 v 2.4 v row address column address read write
MB91110 series 79 (9) high speed page read/write cycle of the normal dram mode (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) * : when q4 cycle is extended for 1 cycle, add t cyc time to this rating. parameter sym- bol pin name condi- tions value unit remarks min. max. ras delay time t clrah clk, ras ? ? 10 ns cas delay time t clcasl clk cas ? 10 ns cas delay time t clcash ? 10 ns column address delay time t chcav clk a23 to a00 ? 15 ns dw delay time t chdwh clk, dw ? 15 ns output data delay time t chdv1 clk d31 to d16 ? 15 ns cas ? valid data input time t cldv cas d31 to d16 ? t cyc - 17 ns * cas - ? data holding time t cadh 0 ? ns
MB91110 series 80 0.8 v 2.4 v 0.8 v 2.4 v t clcash 0.8 v 2.4 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v t chdwh t chdv1 0.8 v 2.4 v d31 ~ d16 clk d31 ~ d16 ras cas a23 ~ a00 dw q4 q5 2.4 v 0.8 v q5 0.8 v q4 q5 2.4 v 0.8 v t clrah 2.4 v 2.4 v 0.8 v t clcasl 0.8 v 2.4 v t cadh t chcav t cldv column address column address column address read read read write write
MB91110 series 81 (10) single dram timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) parameter sym- bol pin name condi- tions value unit remarks min. max. ras delay time t clrah2 clk ras ? ? 10 ns ras delay time t chral2 ? 10 ns cas delay time t chcasl2 clk cas ? n / 2 t cyc + 8 ns cas delay time t chcash2 ? 10 ns row address delay time t chrav2 clk a23 to a00 ? 15 ns column address delay time t chcav2 ? 15 ns dw delay time t chdwl2 clk dw ? 15 ns dw delay time t chdwh2 ? 15 ns output data delay time t chdv2 clk d31 to d16 ? 15 ns cas ? valid data input time t cldv2 cas d31 to d16 ? (1 - n / 2) t cyc - 17 ns cas - ? data holding time t cadh2 0 ? ns
MB91110 series 82 column-2 t chcash2 t chral2 t chdwh2 t chdwl2 t chdv2 t chdv2 d31 ~ d16 (write) clk d31 ~ d16 (read) ras cas a23 ~ a00 dw (write) q2 q3 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v q1 q4s q4s q4s t cadh2 t cldv2 t chrav2 t chcav2 t chcasl2 t cyc 2.4 v 2.4 v t clrah2 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v column-0 column-1 * 2 * 1 row address read-0 read-1 read-2 write-0 write-1 write-2 *1 : q4s cycle indicates the q4sr (read) or q4sw (write) cycle of the single dram cycle. *2 : indicates when a bus cycle is started from the high-speed page mode.
MB91110 series 83 (11) hyper dram timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) parameter sym- bol pin name condi- tions value unit remarks min. max. ras delay time t clrah3 clk ras ? ? 10 ns ras delay time t chral3 ? 10 ns cas delay time t chcasl3 clk cas ? n / 2 t cyc + 8 ns cas delay time t chcash3 ? 10 ns row address delay time t chrav3 clk a23 to a00 ? 15 ns column address delay time t chcav3 ? 15 ns rd delay time t chrl3 clk rd ? 15 ns rd delay time t chrh3 ? 15 ns rd delay time t clrl3 ? 15 ns dw delay time t chdwl3 clk dw ? 15 ns dw delay time t chdwh3 ? 15 ns output data delay time t chdv3 clk d31 to d16 ? 15 ns cas ? valid data input time t cldv3 cas d31 to d16 ? t cyc - 20 ns cas ? data holding time t cadh3 0 ? ns
MB91110 series 84 t chcash3 t chral3 t chdwh3 t chdwl3 t chdv3 t chdv3 d31 ~ d16 (write) clk d31 ~ d16 ( read) ras cas rd ( read) a23 ~ a00 dw (write) q2 q3 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v 2.4 v 0.8 v q1 q4h q4h q4h 0.8 v t cadv3 t cldv3 t chrav3 t clrl3 0.8 v t chrl3 t chcasl3 t cyc 2.4 v t clrah3 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 2.4 v 2.4 v 0.8 v column-0 column-1 * 2 * 2 * 1 column-2 t chrh3 t chcav3 0.8 v 2.4 v 0.8 v 0.8 v row address read-0 read-1 write-2 write-1 write-0 *1 : q4h cycle indicates the q4hr (read) or q4hw (write) cycle of the hyper dram cycle. *2 : indicates when a bus cycle is started from the high-speed page mode.
MB91110 series 85 (12) cbr refresh (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) parameter sym- bol pin name condi- tions value unit remarks min. max. ras delay time t clrah clk ras ? ? 10 ns ras delay time t chral ? 10 ns cas delay time t clcasl clk cas ? 10 ns cas delay time t clcash ? 10 ns t clcash clk ras cas 0.8 v 0.8 v r4 2.4 v 0.8 v t clrah r3 r2 r1 0.8 v 2.4 v 2.4 v 2.4 v 0.8 v t chral t clcasl dw t cyc
MB91110 series 86 (13) self refresh (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) parameter sym- bol pin name condi- tions value unit remarks min. max. ras delay time t clrah clk ras ? ? 10 ns ras delay time t chral ? 10 ns cas delay time t clcasl clk cas ? 10 ns cas delay time t clcash ? 10 ns clk ras cas 0.8 v t chral sr1 2.4 v t chcasl t clrah 2.4 v sr2 2.4 v sr3 0.8 v 0.8 v sr3 0.8 v 2.4 v 2.4 v t clcash t cyc
MB91110 series 87 (14) uart timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) notes : this is the ac standard in the case of clk synchronous mode. t cycp is the cycle time of the peripheral system clock. parameter symbol pin name conditions value unit remarks min. max. serial clock cycle time t scyc ? internal shift clock mode 8 t cycp ? ns sclk ? sout delay time t slov ?- 80 80 ns valid sin ? sclk - t ivsh ? 100 ? ns sclk - ? valid sin holding lock t shix ? 60 ? ns serial clock h pulse width t shsl ? external shift clock mode 4 t cycp ? ns serial clock l pulse width t slsh ? 4 t cycp ? ns sclk ? sout delay time t slov ?? 150 ns valid sin ? sclk - t ivsh ? 60 ? ns sclk - ? valid sin holding lock t shix ? 60 ? ns
MB91110 series 88 ? internal shift clock mode ? external shift clock mode sclk sout sin t scyc t slov t ivsh t shix v oh v ol v ol v oh v ol v ih v il v ih v il sclk sout sin t slov t slsh t shsl t ivsh t shix v oh v ol v ih v ih v il v il v il v ih v il v ih
MB91110 series 89 (15) trigger system input timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) note : t cycp is the cycle time of the peripheral system clock. parameter sym- bol pin name condi- tions value unit remarks min. max. a/d initiation trigger input time t trg atg ? 5 t cycp ? ns ppg initiation trigger input time trg0 to trg5 ns atg trg0 ~ trg5 t trg v il v il
MB91110 series 90 (16) dma controller timing (v cc 5 = 5 v 10 % , v cc 3 = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) parameter sym- bol pin name condi- tions value unit remarks min. max. dreq input pulse width t drwh dreq0 to dreq2 ? 2 t cyc ? ns dack delay time (normal bus) (normal dram) t cldl clk dack0 to dack2 ? 6ns t cldh ? 6ns eop delay time (normal bus) (normal dram) t clel clk deop0 to deop2 ? 6ns t cleh ? 6ns dack delay time (single dram) (hyper dram) t chdl clk dack0 to dack2 ? n / 2 t cyc ns t chdh ? 6ns eop delay time (single dram) (hyper dram) t chel clk deop0 to deop2 ? n / 2 t cyc ns t cheh ? 6ns clk dreq0 ~ dreq2 2.4 v 2.4 v 2.4 v 2.4 v 0.8 v 0.8 v 0.8 v 0.8 v 2.4 v 2.4 v dack0 ~ dack2 deop0 ~ deop2 dack0 ~ dack2 deop0 ~ deop2 (single dram) (hyper dram) t cyc t drwh t cldl t clel t chdl t chel t cldh t cleh t chdh
MB91110 series 91 5. a/d converter electrical characteristics (v cc 5 = 5 v 10 % , v cc 3 = av cc = avrh = 3.3 v 5 % , v ss = av ss = avrl = 0 v, t a = 0 c to + 70 c) *1 : in case of v cc 3 = av cc = 3.3 v 5%, machine clock 25 mhz *2 : this is the current in the case that the a/d converter is not activated and the cpu is stopped (in case of v cc 3 = a vcc = avrh = 3.465 v) notes : as the avrh becomes smaller, the tolerance becomes relatively larger. output impedance of external circuits other than analog input must be used under the following condition. output impedance of external circuits < 7 k w if the output impedance of the external circuits is too high, the sampling time for the analog voltage may be insufficient. parameter sym- bol pin name value unit min. typ. max. resolution ?? ? 10 10 bit conversion error ?? ? ? 3.0 lsb linearity error ?? ? ? 2.5 lsb differential linearity error ?? ? ? 1.9 lsb zero transition error v ot an0 to an7 - 1.5 + 0.5 + 2.5 lsb full-scale transition error v fst an0 to an7 avrh - 4.5 avrh - 1.5 avrh + 0.5 lsb conversion time ?? 5.6* 1 ??m s analog port input current i ain an0 to an7 ? 0.1 10 m a analog input voltage v ain an0 to an7 av ss ? avrh v standard voltage ? avrh av ss ? av cc v power supply current i a av cc ? 4 ? ma i ah ?? 5* 2 m a standard voltage current supplied i r avrh ? 110 ?m a i rh ?? 5* 2 m a tolerance between channels ? an0 to an7 ?? 4lsb
MB91110 series 92 r on1 : 5 k w r on2 : 620 w r on3 : 620 w r on4 : 620 w c 0 : 2 pf c 1 : 2 pf r on1 r on2 r on3 r on4 c 0 c 1 analog input sample holding circuit comparator note : figures described above should be considered as standard.
MB91110 series 93 definition of a/d converter terms ? resolution analog changes that can be identified by a/d converter ? linearity error difference between the straight line linking the zero transition point (00 0000 0000 ?? 00 0000 0001) to the full-scale transition point (11 1111 1110 ?? 11 1111 1111) and actual conversion characteristics. ? differential linearity error difference compared to the ideal input voltage value required to change the output code 1lsb 3ff 3fe 3fd 004 003 002 001 avrl avrh {1 lsb (n - 1) + v ot } v nt (actual measured value) v ot (actual measured value) digital output actual conversion characteristics ideal characteristics analog input actual conversion characteristics v fst (actual measured value) n - 1 avrl avrh n - 2 n n + 1 actual conversion characteristics actual conversion characteristics ideal characteristics v nt (actual measured value) v (n + 1)t (actual measured value) digital output analog input linearity error of digital output n = v nt - {1 lsb (n - 1) + v ot } 1 lsb [lsb] differential linearity error of digital output n = v ( n + 1 ) t - v nt 1 lsb - 1 1 lsb = v fst - v ot 1022 [v] 1 lsb (ideal value) = avrh - avrl 1024 [v] v ot : voltage with digital output transferred from (000) h to (001) h v fst : voltage with digital output transferred from (3fe) h to (3ff) h v nt : voltage with digital output transferred from (n - 1) h to n [lsb] [linearity error] [differential linearity error]
MB91110 series 94 ? total error this indicates the difference between the actual and theoretical values and includes zero transition, full-scale transition and linearity error. 3ff 3fe 3fd 004 003 002 001 avrl avrh 1.5 lsb 0.5 lsb {1 lsb (n - 1) + 0.5 lsb} digital output analog input actual conversion characteristics actual conversion characteristics ideal characteristics v nt (actual measured value) total tolerance of digital output n = v nt - {1 lsb (n - 1) + 0.5 lsb} 1 lsb [lsb] v ot (ideal value) = avrl + 0.5 lsb [v] v fst (ideal value) = avrh - 1.5 lsb [v] v nt : voltage with digital output transferred from (n - 1) h to n [total error]
MB91110 series 95 n n n n instructions (165 instructions) 1. how to read instruction set summary (1) names of instructions instructions marked with * are not included in cpu specifications. these are extended instruction codes added/extended at assembly language levels. (2) addressing modes specified as operands are listed in symbols. refer to 2. addressing mode symbols for further information. (3) instruction types (4) hexa-decimal expressions of instructions (5) the number of machine cycles needed for execution a: memory access cycle and it has possibility of delay by ready function. b: memory access cycle and it has possibility of delay by ready function. if an object register in a ld operation is referenced by an immediately following instruction, the interlock function is activated and number of cycles needed for execution increases. c: if an immediately following instruction operates to an object of r15, ssp or usp in read/write mode or if the instruction belongs to instruction format a group, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. d: if an immediately following instruction refers to mdh/mdl, the interlock function is activated and number of cycles needed for execution increases by 1 to make the total number of 2 cycles needed. for a, b, c and d, minimum execution cycle is 1. (6) change in flag sign ? flag change c : change C : no change 0:clear 1:set ? flag meanings n : negative flag z:zero flag v:over flag c:carry flag (7) operation carried out by instruction mnemonic type op cyc nzvc operation remarks add rj, ri * add #s5, ri , , a c , , a6 a4 , , 1 1 , , cccc cccc , , ri + rj ? ri ri + s5 ? ri , , (1) (2) (3) (4) (5) (6) (7)
MB91110 series 96 2. addressing mode symbols ri : register direct (r0 to r15, ac, fp, sp) rj : register direct (r0 to r15, ac, fp, sp) r13 : register direct (r13, ac) ps : register direct (program status register) rs : register direct (tbr, rp, ssp, usp, mdh, mdl) cri : register direct (cr0 to cr15) crj : register direct (cr0 to cr15) #i8 : unsigned 8-bit immediate (C128 to 255) note: C128 to C1 are interpreted as 128 to 255 #i20 : unsigned 20-bit immediate (C0x80000 to 0xfffff) note: C0x7ffff to C1 are interpreted as 0x7ffff to 0xfffff #i32 : unsigned 32-bit immediate (C0x80000000 to 0xffffffff) note: C0x80000000 to C1 are interpreted as 0x80000000 to 0xffffffff #s5 : signed 5-bit immediate (C16 to 15) #s10 : signed 10-bit immediate (C512 to 508, multiple of 4 only) #u4 : unsigned 4-bit immediate (0 to 15) #u5 : unsigned 5-bit immediate (0 to 31) #u8 : unsigned 8-bit immediate (0 to 255) #u10 : unsigned 10-bit immediate (0 to 1020, multiple of 4 only) @dir8 : unsigned 8-bit direct address (0 to 0xff) @dir9 : unsigned 9-bit direct address (0 to 0x1fe, multiple of 2 only) @dir10 : unsigned 10-bit direct address (0 to 0x3fc, multiple of 4 only) label9 : signed 9-bit branch address (C0x100 to 0xfc, multiple of 2 only) label12 : signed 12-bit branch address (C0x800 to 0x7fc, multiple of 2 only) label20 : signed 20-bit branch address (C0x80000 to 0x7ffff) label32 : signed 32-bit branch address (C0x80000000 to 0x7fffffff) @ri : register indirect (r0 to r15, ac, fp, sp) @rj : register indirect (r0 to r15, ac, fp, sp) @(r13, rj) : register relative indirect (rj: r0 to r15, ac, fp, sp) @(r14, disp10) : register relative indirect (disp10: C0x200 to 0x1fc, multiple of 4 only) @(r14, disp9) : register relative indirect (disp9: C0x100 to 0xfe, multiple of 2 only) @(r14, disp8) : register relative indirect (disp8: C0x80 to 0x7f) @(r15, udisp6) : register relative (udisp6: 0 to 60, multiple of 4 only) @ri+ : register indirect with post-increment (r0 to r15, ac, fp, sp) @r13+ : register indirect with post-increment (r13, ac) @sp+ : stack pop @Csp : stack push (reglist) : register list
MB91110 series 97 3. instruction types add, addn, cmp, lsl, lsr and asr instructions only msb ty p e a ri lsb rj op ty p e b ty p e c ty p e * c ty p e d ty p e e ty p e f 16 bits 4 4 8 op i8/o8 ri 484 ri u4/m4 op 4 4 8 op s5/u5 ri 754 op u8/rel8/dir/reglist 88 op sub-op ri 844 op rel11 511
MB91110 series 98 4. detailed description of instructions ? add/subtract operation instructions (10 instructions) ? compare operation instructions (3 instructions) ? logical operation instructions (12 instructions) mnemonic type op cycle n z v c operation remarks add rj, ri * add #s5, ri add #i4, ri add2 #i4, ri a c c c a6 a4 a4 a5 1 1 1 1 cccc cccc cccc cccc ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension addc rj, ri a a7 1 cccc ri + rj + c ? ri add operation with sign addn rj, ri * addn #s5, ri addn #i4, ri addn2 #i4, ri a c c c a2 a0 a0 a1 1 1 1 1 CCCC CCCC CCCC CCCC ri + rj ? ri ri + s5 ? ri ri + extu (i4) ? ri ri + extu (i4) ? ri msb is interpreted as a sign in assembly language zero-extension sign-extension sub rj, ri a ac 1 cccc ri C rj ? ri subc rj, ri a ad 1 cccc ri C rj C c ? ri subtract operation with carry subn rj, ri a ae 1 C C C C ri C rj ? ri mnemonic type op cycle n z v c operation remarks cmp rj, ri * cmp #s5, ri cmp #i4, ri cmp2 #i4, ri a c c c aa a8 a8 a9 1 1 1 1 cccc cccc cccc cccc ri C rj ri C s5 ri + extu (i4) ri + extu (i4) msb is interpreted as a sign in assembly language zero-extension sign-extension mnemonic type op cycle n z v c operation remarks and rj, ri and rj, @ri andh rj, @ri andb rj, @ri a a a a 82 84 85 86 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri & = rj (ri) & = rj (ri) & = rj (ri) & = rj word word half word byte or rj, ri or rj, @ri orh rj, @ri orb rj, @ri a a a a 92 94 95 96 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri | = rj (ri) | = rj (ri) | = rj (ri) | = rj word word half word byte eor rj, ri eor rj, @ri eorh rj, @ri eorb rj, @ri a a a a 9a 9c 9d 9e 1 1 + 2a 1 + 2a 1 + 2a ccC C ccC C ccC C ccC C ri ^ = rj (ri) ^ = rj (ri) ^ = rj (ri) ^ = rj word word half word byte
MB91110 series 99 ? bit manipulation arithmetic instructions (8 instructions) *1: assembler generates bandl if result of logical operation u8&0x0f leaves an active (set) bit and generates bandh if u8&0xf0 leaves an active bit. depending on the value in the u8 format, both bandl and bandh may be generated. *2: assembler generates borl if result of logical operation u8&0x0f leaves an active (set) bit and generates borh if u8&0xf0 leaves an active bit. *3: assembler generates beorl if result of logical operation u8&0x0f leaves an active (set) bit and generates beorh if u8&0xf0 leaves an active bit. ? add/subtract operation instructions (10 instructions) *1: divos, div1 32, div2, div3 and div4s are generated. a total instruction code length of 72 bytes. *2: divou and div1 32 are generated. a total instruction code length of 66 bytes. mnemonic type op cycle n z v c operation remarks bandl #u4, @ri (u4: 0 to 0f h ) bandh #u4, @ri (u4: 0 to 0f h ) * band #u8, @ri * 1 c c 80 81 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) & = (f0 h + u4) (ri) & = ((u4<<4) + 0f h ) (ri) & = u8 manipulate lower 4 bits manipulate upper 4 bits borl #u4, @ri (u4: 0 to 0f h ) borh #u4, @ri (u4: 0 to 0f h ) * bor #u8, @ri * 2 c c 90 91 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) | = u4 (ri) | = (u4<<4) (ri) | = u8 manipulate lower 4 bits manipulate upper 4 bits beorl #u4, @ri (u4: 0 to 0f h ) beorh #u4, @ri (u4: 0 to 0f h ) * beor #u8, @ri * 3 c c 98 99 1 + 2a 1 + 2a C CCCC CCCC CCCC (ri) ^ = u4 (ri) ^ = (u4<<4) (ri) ^ = u8 manipulate lower 4 bits manipulate upper 4 bits btstl #u4, @ri (u4: 0 to 0f h ) btsth #u4, @ri (u4: 0 to 0f h ) c c 88 89 2 + a 2 + a 0cCC ccC C (ri) & u4 (ri) & (u4<<4) te s t l o w e r 4 b i t s test upper 4 bits mnemonic type op cycle n z v c operation remarks mul rj, ri mulu rj, ri mulh rj, ri muluh rj, ri a a a a af ab bf bb 5 5 3 3 cccC cccC ccC C ccC C rj ri ? mdh, mdl rj ri ? mdh, mdl rj ri ? mdl rj ri ? mdl 32-bit 32-bit = 64-bit unsigned 16-bit 16-bit = 32-bit unsigned divos ri divou ri div1 ri div2 ri div3 div4s * div ri * 1 * divu ri * 2 e e e e e e 97 C 4 97 C 5 97 C 6 97 C 7 9f C 6 9f C 7 1 1 d 1 1 1 C C CCCC CCCC CcCc CcCc CCCC CCCC CcCc CcCc mdl/ri ? mdl, mdl%ri ? mdh mdl/ri ? mdl, mdl%ri ? mdh step calculation 32-bit/32-bit = 32-bit unsigned
MB91110 series 100 ? shift arithmetic instructions (9 instructions) ? immediate value data transfer instruction (immediate value set/16-bit/32-bit immediate value transfer instruction) (3 instructions) *1: if an immediate value is given in absolute, assembler automatically makes i8, i20 or i32 selection. if an immediate value contains relative value or external reference, assembler selects i32. ? memory load instructions (13 instructions) note: the relations between o8 field of type-b and u4 field of type-c in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 ? o8 = disp8:each disp is a code extension. disp9 ? o8 = disp9>>1:each disp is a code extension. disp10 ? o8 = disp10>>2:each disp is a code extension. udisp6 ? u4 = udisp6>>2:udisp4 is a 0 extension. mnemonic type op cycle n z v c operation remarks lsl rj, ri * lsl #u5, ri lsl #u4, ri lsl2 #u4, ri a c c c b6 b4 b4 b5 1 1 1 1 ccCc ccCc ccCc ccCc ri<>rj ? ri ri>>u5 ? ri ri>>u4 ? ri ri>>(u4 + 16) ? ri logical shift asr rj, ri * asr #u5, ri asr #u4, ri asr2 #u4, ri a c c c ba b8 b8 b9 1 1 1 1 ccCc ccCc ccCc ccCc ri>>rj ? ri ri>>u5 ? ri ri>>u4 ? ri ri>>(u4 + 16) ? ri logical shift mnemonic type op cycle n z v c operation remarks ldi: 32 #i32, ri ldi: 20 #i20, ri ldi: 8 #i8, ri * ldi # {i8 | i20 | i32}, ri * 1 e c b 9f C 8 9b c0 3 2 1 CCCC CCCC CCCC i32 ? ri i20 ? ri i8 ? ri {i8 | i20 | i32} ? ri upper 12 bits are zero- extended upper 24 bits are zero- extended mnemonic type op cycle n z v c operation remarks ld @rj, ri ld @(r13, rj), ri ld @(r14, disp10), ri ld @(r15, udisp6), ri ld @r15 +, ri ld @r15 +, rs ld @r15 +, ps a a b c e e e 04 00 20 03 07 C 0 07 C 8 07 C 9 b b b b b b 1 + a + b CCCC CCCC CCCC CCCC CCCC CCCC cccc (rj) ? ri (r13 + rj) ? ri (r14 + disp10) ? ri (r15 + udisp6) ? ri (r15) ? ri, r15 + = 4 (r15) ? rs, r15 + = 4 (r15) ? ps, r15 + = 4 rs: special-purpose register lduh @rj, ri lduh @(r13, rj), ri lduh @(r14, disp9), ri a a b 05 01 40 b b b CCCC CCCC CCCC (rj) ? ri (r13 + rj) ? ri (r14 + disp9) ? ri zero-extension zero-extension zero-extension ldub @rj, ri ldub @(r13, rj), ri ldub @(r14, disp8), ri a a b 06 02 60 b b b CCCC CCCC CCCC (rj) ? ri (r13 + rj) ? ri (r14 + disp8) ? ri zero-extension zero-extension zero-extension
MB91110 series 101 ? memory store instructions (13 instructions) note: the relations between o8 field of type-b and u4 field of type-c in the instruction format and assembler description from disp8 to disp10 are as follows: disp8 ? o8 = disp8:each disp is a code extension. disp9 ? o8 = disp9>>1:each disp is a code extension. disp10 ? o8 = disp10>>2:each disp is a code extension. udisp6 ? u4 = udisp6>>2:udisp4 is a 0 extension. ? transfer instructions between registers/special-purpose registers transfer instructions (5 instructions) mnemonic type op cycle n z v c operation remarks st ri, @rj st ri, @(r13, rj) st ri, @(r14, disp10) st ri, @(r15, udisp6) st ri, @Cr15 st rs, @Cr15 st ps, @Cr15 a a b c e e e 14 10 30 13 17 C 0 17 C 8 17 C 9 a a a a a a a CCCC CCCC CCCC CCCC CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp10) ri ? (r15 + usidp6) r15 C = 4, ri ? (r15) r15 C = 4, rs ? (r15) r15 C = 4, ps ? (r15) word word word rs: special-purpose register sth ri, @rj sth ri, @(r13, rj) sth ri, @(r14, disp9) a a b 15 11 50 a a a CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp9) half word half word half word stb ri, @rj stb ri, @(r13, rj) stb ri, @(r14, disp8) a a b 16 12 70 a a a CCCC CCCC CCCC ri ? (rj) ri ? (r13 + rj) ri ? (r14 + disp8) byte byte byte mnemonic type op cycle n z v c operation remarks mov rj, ri mov rs, ri mov ri, rs mov ps, ri mov ri, ps a a a e e 8b b7 b3 17 C 1 07 C 1 1 1 1 1 c CCCC CCCC CCCC CCCC cccc rj ? ri rs ? ri ri ? rs ps ? ri ri ? ps transfer between general-purpose registers rs: special-purpose register rs: special-purpose register
MB91110 series 102 ? non-delay normal branch instructions (23 instructions) notes: ? 2/1 in cycle sections indicates that 2 cycles are needed for branch and 1 cycle needed for non-branch. ? the relations between rel8 field of type-d and rel11 field of type-f in the instruction format and assembler discription label9 and label12 are as follows. label9 ? rel8 = (label9 C pc C 2)/2 label12 ? rel11 = (label12 C pc C 2)/2 ? reti must be operated while s flag = 0. mnemonic type op cycle n z v c operation remarks jmp @ri e 97 C 0 2 CCCC ri ? pc call label12 call @ri f e d0 97 C 1 2 2 CCCC CCCC pc + 2 ? rp, pc + 2 + rel11 2 ? pc pc + 2 ? rp, ri ? pc ret e 97 C 2 2 C C C C rp ? pc return int #u8 d 1f 3+3a C C C C ssp C = 4, ps ? (ssp), ssp C = 4, pc + 2 ? (ssp), 0 ? i flag, 0 ? s flag, (tbr + 3fc C u8 4) ? pc inte e 9f C 3 3 + 3a C C C C ssp C = 4, ps ? (ssp), ssp C = 4, pc + 2 ? (ssp), 0 ? s flag, (tbr + 3d8 C u8 4) ? pc for emulator reti e 97 C 3 2 + 2a c c c c (r15) ? pc, r15 C = 4, (r15) ? ps, r15 C = 4 bno label9 bra label9 beq label9 bne label9 bc label9 bnc label9 bn label9 bp label9 bv label9 bnv label9 blt label9 bge label9 ble label9 bgt label9 bls label9 bhi label9 d d d d d d d d d d d d d d d d e1 e0 e2 e3 e4 e5 e6 e7 e8 e9 ea eb ec ed ee ef 1 2 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 2/1 CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC non-branch pc + 2 + rel8 2 ? pc pcif z = = 1 pcif z = = 0 pcif c = = 1 pcif c = = 0 pcif n = = 1 pcif n = = 0 pcif v = = 1 pcif v = = 0 pcif v xor n = = 1 pcif v xor n = = 0 pcif (v xor n) or z = = 1 pcif (v xor n) or z = = 0 pcif c or z = = 1 pcif c or z = = 0
MB91110 series 103 ? branch instructions with delays (20 instructions) notes: ? the relations between rel8 field of type-d and rel11 field of type-f in the instruction format and assembler discription label9 and label12 are as follows. label9 ? rel8 = (label9 C pc C 2)/2 label12 ? rel11 = (label12 C pc C 2)/2 ? delayed branch operation always executes next instruction (delay slot) before making a branch. ? instructions allowed to be stored in the delay slot must meet one of the following conditions. if the other instruction is stored, this device may operate other operation than defined. the instruction described 1 in the other cycle column than branch instruction. the instruction described a, b, c or d in the cycle column. mnemonic type op cycle n z v c operation remarks jmp:d @ri e 9f C 0 1 CCCC ri ? pc call:d label12 call:d @ri f e d8 9f C 1 1 1 CCCC CCCC pc + 4 ? rp, pc + 2 + rel11 2 ? pc pc + 4 ? rp, ri ? pc ret:d e 9f C 2 1 CCCC rp ? pc return bno:d label9 bra:d label9 beq:d label9 bne:d label9 bc:d label9 bnc:d label9 bn:d label9 bp:d label9 bv:d label9 bnv:d label9 blt:d label9 bge:d label9 ble:d label9 bgt:d label9 bls:d label9 bhi:d label9 d d d d d d d d d d d d d d d d f1 f0 f2 f3 f4 f5 f6 f7 f8 f9 fa fb fc fd fe ff 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC CCCC non-branch pc + 2 + rel8 2 ? pc pcif z = = 1 pcif z = = 0 pcif c = = 1 pcif c = = 0 pcif n = = 1 pcif n = = 0 pcif v = = 1 pcif v = = 0 pcif v xor n = = 1 pcif v xor n = = 0 pcif (v xor n) or z = = 1 pcif (v xor n) or z = = 0 pcif c or z = = 1 pcif c or z = = 0
MB91110 series 104 ? direct addressing instructions note: the relations between the dir field of type-d in the instruction format and the assembler description from disp8 to disp10 are as follows: disp8 ? dir + disp8:each disp is a code extension disp9 ? dir = disp9>>1:each disp is a code extension disp10 ? dir = disp10>>2:each disp is a code extension ? resource instructions (2 instructions) ? co-processor instructions (4 instructions) mnemonic type op cycle n z v c operation remarks dmov @dir10, r13 dmov r13, @dir10 dmov @dir10, @r13+ dmov @r13+, @dir10 dmov @dir10, @Cr15 dmov @r15+, @dir10 d d d d d d 08 18 0c 1c 0b 1b b a 2a 2a 2a 2a CCCC CCCC CCCC CCCC CCCC CCCC (dir10) ? r13 r13 ? (dir10) (dir10) ? (r13), r13 + = 4 (r13) ? (dir10), r13 + = 4 r15 C = 4, (dir10) ? (r15) (r15) ? (dir10), r15 + = 4 word word word word word word dmovh @dir9, r13 dmovh r13, @dir9 dmovh @dir9, @r13+ dmovh @r13+, @dir9 d d d d 09 19 0d 1d b a 2a 2a CCCC CCCC CCCC CCCC (dir9) ? r13 r13 ? (dir9) (dir9) ? (r13), r13 + = 2 (r13) ? (dir9), r13 + = 2 half word half word half word half word dmovb @dir8, r13 dmovb r13, @dir8 dmovb @dir8, @r13+ dmovb @r13+, @dir8 d d d d 0a 1a 0e 1e b a 2a 2a CCCC CCCC CCCC CCCC (dir8) ? r13 r13 ? (dir8) (dir8) ? (r13), r13 + + (r13) ? (dir8), r13 + + byte byte byte byte mnemonic type op cycle n z v c operation remarks ldres @ri+, #u4 c bc a C C C C (ri) ? u4 resource ri + = 4 u4: channel number stres #u4, @ri+ c bd a C C C C u4 resource ? (ri) ri + = 4 u4: channel number mnemonic type op cycle n z v c operation remarks copop #u4, #cc, crj, cri copld #u4, #cc, rj, cri copst #u4, #cc, crj, ri copsv #u4, #cc, crj, ri e e e e 9f C c 9f C d 9f C e 9f C f 2 + a 1 + 2a 1 + 2a 1 + 2a CCCC CCCC CCCC CCCC calculation rj ? cri crj ? ri crj ? ri no error traps
MB91110 series 105 ? other instructions (16 instructions) *1: in the addsp instruction, the reference between u8 of type-d in the instruction format and assembler description s10 is as follows. s10 ? s8 = s10>>2 *2: in the enter instruction, the reference between i8 of type-c in the instruction format and assembler description u10 is as follows. u10 ? u8 = u10>>2 *3: if either of r0 to r7 is specified in reglist, assembler generates ldm0. if either of r8 to r15 is specified, assembler generates ldm1. both ldm0 and ldm1 may be generated. *4: the number of cycles needed for execution of ldm0 (reglist) and ldm1 (reglist) is given by the following calculation; a (n C 1) + b + 1 when n is number of registers specified. *5: if either of r0 to r7 is specified in reglist, assembler generates stm0. if either of r8 to r15 is specified, assembler generates stm1. both stm0 and stm1 may be generated. *6: the number of cycles needed for execution of stm0 (reglist) and stm1 (reglist) is given by the following calculation; a n + 1 when n is number of registers specified. mnemonic type op cycle n z v c operation remarks nop e 9f C a 1 C C C C no changes andccr #u8 orccr #u8 d d 83 93 c c cccc cccc ccr and u8 ? ccr ccr or u8 ? ccr stilm #u8 d 87 1 CCCC i8 ? ilm set ilm immediate value addsp #s10 * 1 d a3 1 CCCC r15 + = s10 add sp instruction extsb ri extub ri extsh ri extuh ri e e e e 97 C 8 97 C 9 97 C a 97 C b 1 1 1 1 CCCC CCCC CCCC CCCC sign extension 8 ? 32 bits zero extension 8 ? 32 bits sign extension 16 ? 32 bits zero extension 16 ? 32 bits ldm0 (reglist) ldm1 (reglist) * ldm (reglist) * 3 d d 8c 8d * 4 * 4 C CCCC CCCC CCCC (r15) ? reglist, r15 increment (r15) ? reglist, r15 increment (r15 + +) ? reglist, load-multi r0 to r7 load-multi r8 to r15 load-multi r0 to r15 stm0 (reglist) stm1 (reglist) * stm2 (reglist) * 5 d d 8e 8f * 6 * 6 C CCCC CCCC CCCC r15 decrement, reglist ? (r15) r15 decrement, reglist ? (r15) reglist ? (r15 + +) store-multi r0 to r7 store-multi r8 to r15 store-multi r0 to r15 enter #u10 * 2 d 0f 1+a CCCC r14 ? (r15 C 4), r15 C 4 ? r14, r15 C u10 ? r15 entrance processing of function leave e 9f C 9 b C C C C r14 + 4 ? r15, (r15 C 4) ? r14 exit processing of function xchb @rj, ri a 8a 2a C C C C ri ? temp, (rj) ? ri, temp ? (rj) for semafo management byte data
MB91110 series 106 ? 20-bit normal branch macro instructions *1: call20 (1) if label20 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call @ri *2: bra20 (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp @ri *3: bcc20 (beq20 to bhi20) (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp @ri false: mnemonic operation remarks * call20 label20, ri next instruction address ? rp, label20 ? pc ri: temporary register * 1 * bra20 label20, ri * beq20 label20, ri * bne20 label20, ri * bc20 label20, ri * bnc20 label20, ri * bn20 label20, ri * bp20 label20, ri * bv20 label20, ri * bnv20 label20, ri * blt20 label20, ri * bge20 label20, ri * ble20 label20, ri * bgt20 label20, ri * bls20 label20, ri * bhi20 label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
MB91110 series 107 ? 20-bit delayed branch macro instructions *1: call20:d (1) if label20 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri call:d @ri *2: bra20:d (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:20 #label20, ri jmp:d @ri *3: bcc20:d (beq20:d to bhi20:d) (1) if label20 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label20 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:20 #label20, ri jmp:d @ri false: mnemonic operation remarks * call20:d label20, ri next instruction address + 2 ? rp, label20 ? pc ri: temporary register * 1 * bra20:d label20, ri * beq20:d label20, ri * bne20:d label20, ri * bc20:d label20, ri * bnc20:d label20, ri * bn20:d label20, ri * bp20:d label20, ri * bv20:d label20, ri * bnv20:d label20, ri * blt20:d label20, ri * bge20:d label20, ri * ble20:d label20, ri * bgt20:d label20, ri * bls20:d label20, ri * bhi20:d label20, ri label20 ? pc if (z = = 1) then label20 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
MB91110 series 108 ? 32-bit normal macro branch instructions *1: call32 (1) if label32 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call label12 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call @ri *2: bra32 (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp @ri *3: bcc32 (beq32 to bhi32) (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp @ri false: mnemonic operation remarks * call32 label32, ri next instruction address ? rp, label32 ? pc ri: temporary register * 1 * bra32 label32, ri * beq32 label32, ri * bne32 label32, ri * bc32 label32, ri * bnc32 label32, ri * bn32 label32, ri * bp32 label32, ri * bv32 label32, ri * bnv32 label32, ri * blt32 label32, ri * bge32 label32, ri * ble32 label32, ri * bgt32 label32, ri * bls32 label32, ri * bhi32 label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
MB91110 series 109 ? 32-bit delayed macro branch instructions *1: call32:d (1) if label32 C pc C 2 is between C0x800 and +0x7fe, instruction is generated as follows; call:d label12 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri call:d @ri *2: bra32:d (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bra:d label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; ldi:32 #label32, ri jmp:d @ri *3: bcc32:d (beq32:d to bhi32:d) (1) if label32 C pc C 2 is between C0x100 and +0xfe, instruction is generated as follows; bcc:d label9 (2) if label32 C pc C 2 is outside of the range given in (1) or includes external reference symbol, instruction is generated as follows; bxcc false xcc is a revolt condition of cc ldi:32 #label32, ri jmp:d @ri false: mnemonic operation remarks * call32:d label32, ri next instruction address + 2 ? rp, label32 ? pc ri: temporary register * 1 * bra32:d label32, ri * beq32:d label32, ri * bne32:d label32, ri * bc32:d label32, ri * bnc32:d label32, ri * bn32:d label32, ri * bp32:d label32, ri * bv32:d label32, ri * bnv32:d label32, ri * blt32:d label32, ri * bge32:d label32, ri * ble32:d label32, ri * bgt32:d label32, ri * bls32:d label32, ri * bhi32:d label32, ri label32 ? pc if (z = = 1) then label32 ? pc ifs/z = = 0 ifs/c = = 1 ifs/c = = 0 ifs/n = = 1 ifs/n = = 0 ifs/v = = 1 ifs/v = = 0 ifs/v xor n = = 1 ifs/v xor n = = 0 ifs/(v xor n) or z = = 1 ifs/(v xor n) or z = = 0 ifs/c or z = = 1 ifs/c or z = = 0 ri: temporary register * 2 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3 ri: temporary register * 3
MB91110 series 110 n n n n ordering information part number package remarks mb911110pmt2 144-pin plastic lqfp (fpt-144p-m08) mb911v110cr pga-299c-a01
MB91110 series 111 n n n n package dimension 144-pin plastic lqfp (fpt-144p-m08) dimensions in mm (inches) . c 2000 fujitsu limited f144019s-c-2-4 details of "a" part 0.25(.010) (stand off) (.004?004) 0.10?.10 (.024?006) 0.60?.15 (.020?008) 0.50?.20 1.50 +0.20 ?.10 +.008 ?004 .059 0?8 0.50(.020) "a" 0.08(.003) 0.145?.055 (.006?002) lead no. 1 36 index 37 72 73 108 109 144 0.22?.05 (.009?002) m 0.08(.003) 20.00?.10(.787?004)sq 22.00?.20(.866?008)sq (mounting height)
MB91110 series fujitsu limited for further information please contact: japan fujitsu limited corporate global business support division electronic devices shinjuku dai-ichi seimei bldg. 7-1, nishishinjuku 2-chome, shinjuku-ku, tokyo 163-0721, japan tel: +81-3-5322-3347 fax: +81-3-5322-3386 http://edevice.fujitsu.com/ north and south america fujitsu microelectronics, inc. 3545 north first street, san jose, ca 95134-1804, u.s.a. tel: +1-408-922-9000 fax: +1-408-922-9179 customer response center mon. - fri.: 7 am - 5 pm (pst) tel: +1-800-866-8608 fax: +1-408-922-9179 http://www.fujitsumicro.com/ europe fujitsu microelectronics europe gmbh am siebenstein 6-10, d-63303 dreieich-buchschlag, germany tel: +49-6103-690-0 fax: +49-6103-690-122 http://www.fujitsu-fme.com/ asia pacific fujitsu microelectronics asia pte. ltd. #05-08, 151 lorong chuan, new tech park, singapore 556741 tel: +65-281-0770 fax: +65-281-0220 http://www.fmap.com.sg/ korea fujitsu microelectronics korea ltd. 1702 kosmo tower, 1002 daechi-dong, kangnam-gu,seoul 135-280 korea tel: +82-2-3484-7100 fax: +82-2-3484-7111 f0101 ? fujitsu limited printed in japan all rights reserved. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. any semiconductor devices have inherently a certain rate of failure. you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade control law of japan, the prior authorization by japanese government should be required for export of those products from japan.

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